Assemblydissassembly

MODEL 2800-2815

NOTE: These two screws MUST be replaced ¡n the correct places.

MODEL 2820-2823

KEYBOARD REMOVAL

KEYBOARD REMOVAL

00 CM

"53

"O

Arp Minus Noise Mixer

00 CM

"53

"O

Scph 1200 Controller Board

SECTION 2 CIRCUIT DESCRIPTIONS (Board A-1)

2.1.1 Trigger Circuit

Each key on the keyboard has its own capacitor-resistor-diode network. The capacitors are normally charged to +15 volts until a key is depressed at which time the capacitor discharges through the diode creating a trigger pulse on the trigger bus rod. Q1 through Q4 are a monostable multivibrator which delays the trigger pulses 15 milliseconds to allow the gate and CV to stabilize.

2.1.2 PITCH BEND

P1, the pitch bend control, supplies a control voltage to both VCOs on Board B. CR4 and CR5 create a 'dead' zone when the control is centered.

2.1.3. CURRENT SOURCE

Q5 supplies constant current to a resistor divider chain made up of thirty-six 100 ohm resistors connected in series. The CV contacts are located at the junction of each of the 100 ohm resistors to supply a specific voltage to the control voltage memory when a key is depressed. There is a three volt drop across the entire resistor chain, or one volt per octave. T1, the Volts/Octave trimmer, adjusts the current through the resistor chain to produce the correct voltage drop across the keyboard.

2.1.4. TRANSPOSE SWITCH

Half of the transpose switch is connected to the bottom end of the resistor chain to, in effect, add two or four octaves worth of resistance (about 1200 or 2400 ohms) to the resistor chain. This raises the control voltage level supplied to the CV memory. The following chart summarizes the CV output for low 'C' and high 'C' on the keyboard for each of the transpose switch positions:

TRANSPOSE

LOW

HIGH

SWITCH:

'C

4C'

DOWN 2 OCT.

0 V

+3 V

NORMAL

+ 2 V

+ 5 V

UP 2 OCT.

+4 V

+ 7 V

The remaining half of the transpose switch compensates the second voice control voltage for the difference in the resistor chain resistance.

2.1.5 CV Memory Circuit

Q6 and A1A are a FET input op amp which buffers the voltage from the keyboard CV bus and supplies it to the memory circuit through R23 and CR3.

When a key is depressed, +15 volts is supplied from the keyboard gate through CR2 and R21 which reverse biases CR3 and allows Q7 to conduct. The control voltage from A1A is then allowed to charge the memory capacitor, C8. When a key is released, Q7 turns off to prevent C8 from discharging. Q8 and A1B are a FET op amp which buffers the control voltage on C8 and supplies it to the control input of VCO 1 and VCO 2 on Board B and to the VCF on Board C.

2.1.6 Second Voice CV Generator

When two or more keys are depressed, a section of the resistor chain is effectively shorted out which drops the voltage at the top end of the resistor chain. This voltage drop corresponds to the 'voltage difference' between two held keys. A2A is a unity gain buffer which monitors the voltage at the top of the resistor chain and supplies it to A2B. A2B sums the voltage from A2A with the voltage supplied by R31 and R30. These resistors are selected to produce zero volts on the output of A2B when either no keys or one key is depressed.

When two or more keys are depressed, the voltage at the top end of the resistor chain drops, which, in turn, decreases the voltage supplied to Z2B. Z2B then supplies the difference voltage to the control input of VCO 2 where it is summed with the control voltage from the CV memory circuit. This summation allows VCO 2 to be controlled by the highest key depressed. Since VCO 1 is fed the control voltage from the CV memory only, its pitch is controlled by the lowest key depressed.

2.1.7 Noise Generator

The noise generator circuit produces 10VPP white and pink noise signals which are supplied to the VCF audio input and the S/H mixer. The noise is obtained by amplifying a reversed biased transistor junction (Q9) in avalanche breakdown. Q9 is a transistor selected for optimum avalanche characteristics; and therefore, has good noise producing capability. A3 amplifies and clips the noise signal. A3 filters the noise to provide pink noise to the VCF and S/H.

The sample and hold circuit provides a DC voltage output by sampling and storing the instantaneous voltage level of signals on its input each time a trigger pulse is provided. This stored voltage is held until the next trigger pulse occurs. Signals which are to be sampled and applied to pin 3 of A3. A3 is an operational transconductance amplifier (OTA), which is used as a gated voltage follower: when a pulse is applied to pin 5 of Z3, capacitor C7 charges to the voltage level on pin 3. This voltage level is held until another pulse is applied to pin 5. Q3 buffers the voltage on C7 and supplies it to A2B through the lag slider (P16). A2B is a unity gain buffer. The sample and hold output is supplied to the control inputs of VCO 1 and VC02 and to the VCF on Board C.

2.2.2 Low Frequency Oscillator (LFO)

The LFO produces a triangle and square wave output in a frequency range from about .1 Hz to 25 Hz. Z1A and C3 are an integrator which charges from current passing through R11. Z1B is a hysteretic switch whose output switches from -15 volts to +15 volts when the output of Z1A reaches +5 volts. This then reverses the direction of current through R11 and the rate control (Z5) and thus the direction of integration at the output of Z1A. When the output of Z1A reaches -5 volts, the output of Z1B switches back to -15 volts and the cycle repeats.

An LFO reset pulse is supplied from the keyboard every time a key is depressed. Q1 and Q2 are turned on momentarily by the keyboard trigger pulse to discharge the integrating capacitor (C3) thus reinitializing the LFO to zero.

2.2.3 Voltage Controlled Oscillators (VCO)

Oscillator circuit (VCO 1 & 2): Control voltages from the keyboard, initial frequency and fine tune sliders, pitch bend (2800 only) and both FM input sliders are summed on the base of 04. Q4 and Q5 are a linear voltage to exponential current generator; for every volt applied from the keyboard, the current through Q5 will double. C12 is the integrating capacitor; it is initially charged to +15 volts and discharges through R51 and 05 toward ground. 05 determines the discharge time of the capacitor and therefore the period of oscillation. Z1D is a CMOS nand gate used as a comparator. When the voltage on pin 12 of Z1D falls below +7.5 volts, the output of Z1 (pin 11) changes from zero volts to +15 volts which turns on 010, 07 and Q6. Q6 recharges the integrating capacitor (C12) to +15 volts to start the cycle over again.

08 buffers the sawtooth wave on C12 and supplies it to the sawtooth to pulse converter and Q9, the output emitter follower. The oscillator circuit for VCO 2 is the same as VCO 1. When the 'SYNC' switch is on, the reset pulse from VCO 1 is applied to Z2D which causes VCO 2 to reset at the same time as VCO 1, regardless of the voltage level on pin 12 of Z2D. The waveform on the output of VCO 2 is then synchronized with VCO 1.

Sawtooth to square wave converter: Z1A and Z1B are a R-S flip-flop with pin 8 used as a comparator. The reset pulse from Z1C is supplied to pin 1 and the sawtooth wave to pin 8. As the sawtooth wave is raised above the zero reference by the pulse width trimmer and sliders (T2, P8 and P9) the flip-flop will change state on a different point of the sawtooth slope resulting in a different pulse width. With all of the pulse width sliders on the front panel at minimum, the pulse wave should be square (50% duty cycle). The pulse wave output is supplied to the audio input of the VCF on Board C and to the ring modulator circuit on Board B.

2.2.4 Ring Modulator

The ring modulator utilizes two CMOS nand gates (Z1B and Z2B) and 018 in an exclusive 'or' function. Square waves from VCO 1 and VCO 2 are supplied to pin 5 of Z1 and Z2 and the output is taken from the emitter of 018.

GATE TRUTH TABLES

NAND GATE EXCLUSIVE OR

A

B

C

A

B

C

0

0

1

0

0

0

0

1

1

0

1

1

1

0

1

0

1

1

1

1

0

1

1

VCO 2

RING MODULATOR OUTPUT

2.3.1 Voltage Controlled Filter (VCF)

Audio signals from both VCOs, the ring modulator, and the noise generator are applied to the audio input of the voltage controlled filter (pin 1,4023) through C1. Control voltage from the S/H, LFO, KYBD CV, and the envelope generators are summed and inverted by A1. The control input of the VCF accepts negative going control voltages; as the voltage on pin 3 of the 4023 module is decreased, the filter cutoff increases. Signals on the output of the VCF (pin 10) are fed back to the resonance input (pin 2) via the resonance slider, (P2).

2.3.2 Voltage Controlled Amplifier (VCA)

Audio signals from the VCF are processed through the high pass filter (C3, R13 and P3) and connected to the noninverting input of A3. A3 is an operational transconductance amplifier (OTA) whose gain is a function of the current supplied to pin 5. Control voltages from the two envelope generators and the VCA gain slider are connected to Q1 which supplies current to the OTA. T2, the control reject trimmer, balances the inputs of the OTA to minimize the effect of control voltages on the audio output of the VCA.

2.3.3 AR Envelope Generator

The Attack-Release envelope generator produces a control voltage with variable rise and fall times. It is used to control the VCF or the VCA. When a gate voltage is supplied by the keyboard or the LFO through S10, 04 turns on which charges capacitor C7 through P5, R32 and CR5. The position of P5 (Attack Slider) determines the time C7 takes to charge up. When the gate voltage is removed, 04 turns off which allows 05 to turn on. The voltage on C7 then discharges through CR6, P6, R31, and 05. P6 (Release slider) sets the release time. 06 and 07 buffer the voltage on C7 and supply it to the VCA and VCF.

2.3.4 ADSR Envelope Generator

The Attack-Decay-Sustain-Release envelope generator produces a control voltage with variable rise and fall times. It is used to control the VCF or the VCA and a gate and trigger signal must be supplied from the keyboard or LFO to start the ADSR voltage rising.

Attack: When a gate signal (+10 volts) is supplied through S8, Q8, 09 and Q10 turn on which then allows Q16 to turn off. With Q16 off, a trigger applied through C9 and R55 will momentarily turn

GATE

II TRIGGER

ATTACK /

1 ADSR OUTPUT

j / SUSTAIN

NOTE: The ADSR is initiated with a gate and trigger voltage, and the AR envelope requires only the gate.

on Q18 and Q17. 017 then supplies +15 volts through CR18, CR19, CR17 and R57 to hold Q18 on. 018 and 017 (the attack latch) now supplies +15 volts through the attack slider (P4), R43, and CR9 and charges up the integrating capacitor, C8.

012, Q13, and Q14 buffer the voltage on C8 and provides it to the VCA and VCF. 015 is the peak detector which monitors the output of the ADSR. When the ADSR voltage reaches its maximum, (about +10 volts), Q15 will turn on and provide this voltage to the base of 016 through CR15. 016 then grounds out the voltage on the base of 018 to unlatch Q18 and Q17 and end the attack portion of the ADSR cycle.

Decay & Sustain: When the attack portion of the ADSR cycle has completed, the voltage on C8 is allowed to discharge through CR11, R47, and the decay slider (P15) to the emitter of 011. The sustain slider (P16) sets the voltage level on the base of 011. When the voltage level on the emitter of 011 falls below the level on the base, Q11 turns off and prevents the voltage on 08 from discharging further.

Release: When the gate is removed, the remaining voltage on C8 is discharged to ground through CR10, R44 and the release slider (P17).

2.4.1 Keyboard Current Source

The keyboard current source supplies constant current through thirty-six 100 ohm resistors connected in series. These resistors are a voltage divider supplying specific voltages for each key on the keyboard. The top end of the resistor chain is connected to J2-5 and the low end to J2-6. The current source produces a 3 volt drop across the entire keyboard, or 1 volt per octave. The keyboard voltage is fed to the CV memory via the CV bus rod.

Pin 7 of Z2A (high end of the resistor chain) is 0 volts when either no keys or one key is depressed and pin 6 of Z2A (low end of the resistor chain) is +3 volts. When two keys are depressed, the contacts and bus rod short out a section of the resistors in the divider chain which reduces the gain of Z1A thereby raising the voltage on Z2A pin 7. This voltage increase represents the voltage difference between two held keys. When this difference voltage is subsequently added to the control voltage at the control input of VCO 2 (Bd. B), high note priority control over the pitch of VCO 2 is produced.

2.4.2 Control Voltage Memory

Control voltages supplied from the keyboard CV bus are buffered by a unity gain amplifier, Z4A. This voltage is then supplied to the memory capacitor C8 through the portamento slider (R30) and the gating FET (Q3). Q3 is turned on by the gate generator circuit only while a key is depressed. Q4 and Z4B are a FET follower with high input impedance to buffer the voltage on capacitor C8. J3-1 and J3-2 are connected to the portamento footswitch jack so that the portamento slider can be bypassed while the foot-switch is plugged in.

2.4.3 Pitch Bend

Pitch Bend: The Pitch Bend control supplies an offset voltage to Z2B to be summed with the control voltage from Z4B (CV memory). CR3 and CR4 create a 'dead' zone when the control is centered and R27 calibrates the output to exactly plus and minus a volt.

The PPC circuit contains three resistive carbon strips, three conductive rubber strips and various summing resistors. Each end of the carbon strip is connected to a designated voltage source, while each end of the conductive rubber is making contact with the summing resistors. As the PPC button is depressed, the conductive rubber makes contact at various points on the carbon strip which, in turn, provides various degrees of control voltage to the summing resistors. The conductive rubber is tapered so that maximum sensitivity is achieved at the top of the button.

2.4.5 Transpose Switch

Transpose: The transpose switch also supplies an offset voltage to Z2B to be summed with the control voltage from Z4B. R23 calibrates the output to exactly plus and minus 2 volts.

2.4.6 Summing Circuit

Summing: The output of Z4B is +3 volts when high 'C' is depressed and 0 volts when low 'C' is depressed. This control voltage is summed with the offset voltages from the transpose and pitch bend circuits on the input of Z2B. Z2B is a unity gain inverter whose output will be 0 volts with low 'C' depressed (pitch bend and transpose in the normal position) and +3 volts with high 'C' depressed. This voltage is supplied to the VCOs on Board B (pitch control) and the VCF on Board C (filter cutoff control).

2.4.7 Gate Generator

Each gate contact on the keyboard is connected to a 2.2K ohm resistor to ground. When a key is depressed the gate bus voltage drops from +15 volts to about +10 volts which turns on Q1. Q1 supplies two gate signals:

SIGNAL:

Key up:

Key

down:

Location :

CV Memory

-15V

+ 15

V

Q1 coll.

Gate out

0 V

+ 10

V

J4-3

\Key down ^Second key down i AH keys up

: i i i trigger output

2.4.8 Trigger Generator

When a key is depressed, the gate bus voltage drops from +15 volts to about +10 volts. Additional key depressions will drop this voltage still further. These voltage transitions are coupled through capacitor C1 and R4 to Q2. Capacitor C2 is charged to +15 volts by Q2 when a key is depressed. Z1C and Z1D are CMOS nand gates (threshold is +7.5 volts). As C2

charges up, Z1D pin 11 will produce a 10 millisecond pulse (the pulse width is determined by C2) which is supplied to Q8. Q8 will conduct during the fall of the pulse from Z1D to provide a +10 volt trigger pulse (20 microsecond duration) to Board C and B. Trigger pulses from external sources are coupled through C20, Z1A and Z1B to Q8. Z1A and Z1B are connected in parallel to increase drive.

audio input and the S/H mixer. The noise is obtained by amplifying a reversed biased transistor junction (Q5) in avalanche break down. Q5 is a transistor selected for optimum avalanche characteristics and therefore has good noise producing capability. Q6

is a buffer and Z5 amplifies and clips the noise signal. Z3 filters the noise to provide pink noise to the VCF and S/H.

2.4.9 Noise Generator

The noise generator circuit produces 10VPP white and pink noise signals which are supplied to the VCF

NOTE: The more recent model Odysseys employ a zener diode instead of a noise transistor. See the revisions section 1.4.4 for the circuit change.

CIRCUIT DESCRIPTIONS (Board B-ll)

The sample and hold circuit provides a DC voltage output by sampling and storing the instantaneous voltage level of signals on its input each time a trigger pulse is provided. This stored voltage is held until the next trigger pulse occurs. Signals which are to be sampled are applied to pin 3 of Z1A. Z1A amplifies and buffers the signal and supplies it to Q1. When a trigger from either the LFO or the keyboard is received through C3, Q1 conducts just long enough for the memory capacitor (C1) to assume the new voltage level. Then Q1 turns off until another trigger is supplied. Q2 and Z2A are a FET op amp follower which buffers the voltage on C1 and provides it to the lag circuit (R15 and C2) and the output buffer (Z2B).

Noise Generator

Noise Generator

WW

Trigger

S/H Output

t of Z5A. When the output of Z5A reaches -5 volts, the output of Z5B switches back to -15 volts and the cycle repeats. An LFO reset pulse is supplied from Q4 every time a key is depressed. Q5 is turned on momentarily by the LFO reset pulse and discharges the integrating capacitor (C7) thus reinitializing the LFO output to zero.

2.5.3 Voltage Controlled Oscillators (VCO)

Control voltages from the keyboard, initial frequency and fine tune sliders, the sample and hold circuit, LFO square wave and sine wave, and the ADSR are summed on the base of 06. 06 and 07 are a linear voltage to exponential current generator; for every volt applied to the control input of the VCO from the keyboard, Q6 will conduct twice as much current. C11 is the integrating capacitor; it is initially charged to 15 volts and discharges through R61 and 07 towards ground. Q7 determines the discharge current of the capacitor and therefore the period of oscillation. Q9 buffers the voltage on C11 and supplies it to a comparator, Z3B and Z3A. Pin 2 of Z3A is fixed at about +7.5 volts. When the voltage on pin 4 of Z3B decreases to below +7.5 volts, Z3A turns on Q11 which supplies +15 volts to the gate of Q8. Q8 then charges capacitor C11 back to +15 volts to start the cycle over again.

2.5.2 Low Frequency Oscillator (LFO)

The LFO produces a triangle and a square wave output in a frequency range from about .1 Hz to 25 Hz. Z5A and C7 are an integrator which charges from current passing through R33. Z5B is a hysteretic switch whose output switches from -15 volts to +15 volts when the output of Z5A reaches +5 volts. This change in output polarity then reverses the direction of current through R33 and the rate control (R34) and thus the direction of integration of the output

R63. C10 and R59 supply current to 07 as the frequency of the oscillator is increased to prevent the oscillator from going flat due to the recovery time of the circuit. Q12 is a phase splitter which takes the sawtooth from pin 3 of Z3 and supplies it to the oscillator output and the pulse converter. The waveform on the emitter of 012 is 7.5VPP negative going (+7.5 volts offset), and the collecter is about 5VPP positive going (zero referenced).

Sawtooth To Pulse Converter: Z3C and Z3D is a slider (R87) sets the voltage level on the base of Q11. When the voltage level on the emitter of Q11 falls below the level on the base, Q11 turns off and prevents the voltage on Q8 from discharging further.

Release: When the gate is removed, the remaining voltage on C8 is discharged to ground through CR10, R44 and the release slider (R88).

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