464 Ad Filter System

Low-pass and high-pass filters are provided for limiting the bandwidth of the signal being fed to the Analog to Digital converter. The cutoff points of each are individually controllable. Signal arriving at the Master Card at pin 1 of the 10-way ribbon connector is attenuated by MDAC E4. The attenuation is controlled by the data written to the A side of P.I.A. DE5. Op-amp F3 in combination with CMOS switches E1, F1, F5 form the low-pass filter. The cutoff frequency is determined by the...

1

The FAIRLIGHT Graphics Monitor is a high resolution CRT monitor for use with the Fairlight range of microcomputers. It is designed to accept composite video from the Graphics Lightpen Card Q219 and interface the lightpen. The Q219 card is located in the microcomputer mainframe. The display tube is a high-resolution 15 diagonal P3T type which gives a crisp, green image. The large format results in a highly readable display, which means low operator fatigue. An optional high-performance Light Pen...

10

KEYBOARD DISPLAY AND KEYPAD MODULE, CMI-12 The Display and Keypad Module provides a simple user interface with the CMI from the master music keyboard. A 16-switch keypad is scanned by the Keyboard Controller for commands to be sent to the CMI and a 12 digit LED display receives simple messages from the CMI to the user. This section describes the operation of the CMI-12. 6.1 DISPLAY AND KEYPAD OPERTION (Refer to drawing CMI-12-01) The DL-14T6 LED display modules, containing four digits each,...

10r

Due to the stability required of the horizontal oscillator, the 12 V supply is decoupled first by D12 and C60, and then separated by R39 and R4o. R39 provides output power to pin 2 of the IC. R40 feeds pin 1 and also the input and timebase sections, and is further bypassed via C20. Instability of the horizontal timebase may be caused by too much noise on these supplies. Further decoupling is provided by the separate ground connections to both timebase and output sections (pins 16 and 4). This...

11 Picture Tube Handling

CIRCUIT ADJUSTMENT 5.1 PRELIMINARY SET-UP 5.2 POWER SUPPLY CARD,VDU03 6 5.2.1 24V adjust 5.3 MAIN CARD, yD J01 5.3.1 Horizontal Frequency 6 5-3.2 H. Phase 5.3.3 H. Linearity 6 5.3.4 Vertical Frequency 6 5.3.5 Vertical Height & Linearity 7 5.3-6 Focus Adjustment 5.4 CRT CARD, VDU02 5.4.1 Black Level 6. DISASSEMBLY 6.1 TOP COVER REMOVAL 6.2 PICTURE TUBE REPLACEMENT 8 7. LIGHT PEN 7.1 GENERAL DESCRIPTION

11 Preventative Maintenance

The following procedures should be carried out every 1000 hours of operation. 1) Revove the top cover of the Mainframe and clean the mesh above the fans using a vacuum cleaner. 2) Unplug each circuit board, remove dust deposits from components and clean edge connector fingers using a soft cloth and a no-residue solvent such as freon. Check that the polarising key is properly installed in position 7 of each edge connector socket before replacing the cards. 3) Check all cables for signs of...

14 Mechanical Parts Lists 238

14.1 MAINFRAME DRAWING REF DMC0001 14.2 CARD CAGE ASSEMBLY DRAWING REF DMC032 14.3 MAINFRAME REAR PANEL DRAWING REF DMC038 14.4 FRONT PANEL ASSEMBLY DRAWING REF DMC042 241 14.5 TRANSFORMER END PLATE DRAWING REF DMC046 242 14.6 REGULATED POWER SUPPLY DRAWING REF DMC057 243 14.7 FAN ASSEMBLY DRAWING REF DMC066 The C.M.I. Mainframe houses all the data processing and audio generation hardware of the C.M.I. System, including D.C. power supplies and floppy-disk drives. This manual is designed to help...

145 Transformer End Plate Drawing Dmc046

REF.NO PART NO DESCRIPTION ' REMARKS 01 G0051 PLATE C.M.I C CAGE L.H.AND 02 G0066 BRACKET C.M.I AC CONNECTOR 03 G0054 BRACKET C.M.I CAP MTG.AND. 04 G5167 TXFORMER C.M.I 1 ALKAY 05 G5205 CLAMP CORD UTH906 06 G0052 BRKT C.M.I CAP MTG TOP AND 07 G0053 BRKT C.M.I CAP MTG BOT AND. 08 C7& 11 CLIP CAP ELECT SIZE 16 09 G5223 CONNECTOR UTM3191.6R 10 G5222 CONNECTOR UTM3191.6P 11 G5122 CLIP CABLE GREY 3M 12 D2003 RECTIFIER BRIDGE MDA3504 13 G0064 BRACKET C.M.I C CAGE FUSES 14 G5309 HOLDER FUSE FLUSH...

15 11 1 0

RUN Run tests on all active interrupts. Both sequential test (one interrupt at a time) and simultaneous test (triggered simultaneously, arrival checked for correct priority) will be run unless the SEQ or SIM commands have been used. See below. Run will be aborted if error count is exceeded or if the user hits CNTRL ESC (break). REPEAT n Sets the repeat count to n. The original value is printed. A repeat count of zero will continue Indefinitely until aborted. ERROR n Sets maximum error count for...

16 V

Most Of this section is the network required by the horizontal combination IC for timebase generation and compensation. The base frequency is set by C18 quite often problems with stability or frequency adjustment can be solved by replacing this. VR3 enables adjustment either side of the base frequency and can also cause problems. The trimpots are ceramic and rough treatment can fracture them. Be warned - a fracture is not always visible. The frequency and stability of the horizontal trace...

2000jG

A board which is unable to load the system and or MEMDBG can only be debugged by optioning it as Card 1 and installing it along with a healthy board as Card 0. If the faulty board still crashes the system, disable the data driver using option W3 (see Q256 hardware documentation). The eight tests contained in the program should be sufficient to solve most problems on the Q256. However MEMDBG has been written such that debug technicians can easily add their own test loops tailor made to...

23 Slave Keyboard Disassembly And Reassembly

To remove the wooden cover and the CMI-11 switch modules from a 3lave keyboard, follow the same procedures as specified for the master keyboard in sections 2.1.1 and 2.1.3 respectively. 2.3.1 Removal of CMI-14 Slave Interface (Refer to drawing DMC-005) (1) With CMI power off, remove the flat Gable connecting the master- and slave keyboards, if not already done. CAUTION Always turn off CMI power to the master keyboard before connecting or disconnecting the external cable between the master and...

3sx20

A 7.5 V reference is supplied to the base of Q6.Q6 s emitter therefore can set the current flowing through the cathode Chain RT9, R20, R72, Q6, Q7 and C51. R20 varies the voltage on the cathode as this current varies, thus changing the beam current. Three things can influence Q6< s emitter VR2 sets the no-signal beam current i.e. black level. The mixed blanking signal turns Q5 on which shuts down Q6, cutting off the beam current. Video signals turn Q7 on, saturating Q6 and increasing beam...

4

Access to these locations for initialization of the mapsel is decoded by IC 1B, along with the peripheral enable input PENBIN. The output of IC TB is latched on rising BRA by IC 4A (drawing Q256-03) to produce LFC4X. Writing to the mapsel RAM is the most time-critical of all operations on the Q256. Normally the entire current data phase is available to generate the map selection number for the next cycle but when writing, the current data phase must be used to write to the mapsel ram as well....

4102 Communications Port

The front pannel also carries a 10-way flat cable connector, P2, that contains serial communications lines from the Q133 card. The hard Disk Subsystem is in three parts. , The D.M.A. interface that plugs into the C.M.I, buss, the Western Digital Controller that connects to this and the Winchester drive itself. The Q077 card interfaces the Western Digital WD 1002-05 Winchester Floppy Controller, to the C.M.I, buss. This parallel interface allows transfers Via D.M.A. for maximum speed. The cable...

411 Introduction

The Q209 contains the dual 6809 processors, on board processor communication hardware entailing, indivisible instructions, processor readable identification map state, interprocess or interrupts, automatic map switching FUSE register and hardware trace logic to enable single stepping for software debugging. The Dual Processor card multiplexes each processor onto a common address and data buss in an interleaved manner, each processor therefore may simultaneously access the same memory location...

41bottom Cover Removal

Disconnect the Power Signal cable from the 2. Place keyboard face down on smooth surface. 3 Using 'locking type' bladed screwdriver, remove the 4 screws from the base cover. Access is gained through the 4 clearance holes in the bottom cover. 4. Lift off the cover and slide the cord grip out from the bottom cover cutout . 1. Remove bottom cover as in 4.1. 2. Spread cord grip open to release cable. 3- Remove the cable from the Printed Circuit Card by spreading the connector locking lugs apart....

452 Video Timing Logic

All timing is derived from a crystal oscillator and a counter chain. The dot clock is constucted around inverter F2 and the 10.38Mhz crystal. The string of counters at F9 to F11 and Ell to El3 count the dotclock dotclk and with the aid of SROM produce all video related signals. The screen area is organized as 84 bytes on the line and 304 lines in the frame. The actual displayed area is 64 bytes on the line and 256 lines. One byte time is 8 DOTCLK pulses or 770ns. The SROM prom at E10 generates...

47

Mains Neutral, Active and Ground. A.C. Mains supply to Graphics Terminal. Switched by key 3witch on mainframe. This supply is always the same as the local mains potential. Video signal to Graphics Terminal and Light Pen signals to mainframe. Connector Type Cannon 5-pin. Lightpen Hit. T.T.L. level, asserted low. On oscilloscope, appears as a series of low-going pulses about 1uS wide, repeated every 20mS, when the pen is pointed at a bright area of the screen. See figure 8.3a. Lightpen...

471 Introduction

4.8 CMI04 AUDIO MODULE FUNCTIONAL DESCRIPTION 4.8.1 INTRODUCTION 4.8.2 MIXER, LINE DRIVERS 4.8.2.1 Mixer 4.8.2.2 Line Drivers 4.8.3 MONITOR AMP, INPUT AMPS, SYNC IN OUT 4.8.3.1 Monitor Amplifier 4.8.3.2 Input Amplifiers 4.8.3.3 Sync In Out 4.8.4 POWER SUPPLY 4.9 QPSA POWER SUPPLY FUNCTIONAL DESCRIPTION 50 4.9.1 INTRODUCTION 4.9.2 UNREGULATED SUPPLIES 4.9.3 REGULATOR 5 VOLT 18 AMP 4.9.4 + 12 VOLT, 24 VOLT SUPPLIES 51 4.10 Q137 FRONT PANEL FUNCTIONAL DESCRIPTION 52 4.10.1 INTRODUCTION 4.10.1.1...

493 Regulator 5 Volt 18

This regulator is part of the regulator assembly located at the rear of the C.M.I. Card Cage. IC1 is the regulating element of the circuit. Transistor Q2 senses the current drawn by IC1, driving parellel transistors Q3 to Q6. Equal current sharing is ensured by emitter resistors R7-R10. Current limiting is provided by germanium transistor Ql, which uses the drop across sensing resistor R1 as a current sense. Short circuit current is limited to approximately 20 Amps, regulation falling off above...

500r 82r

The signal appears on pin 2 of connector 3. First it is DC isolated by C1 and R1. It is then sent in two directionsone is to the sync separator which we will treat later. The other is to the contrast pot via pin 4 of P3. This divides the signal down to set the size of the luminance signal as desired. This signal then returns thru pin 6 of P3 to pas3 into the buffer stage. It is rare to encounter problems at this stage.

6 Diagnostic Software

6.1 INTRODUCTION TO DIAGNOSTIC SOFTWARE . 73 6.1.1 RUNNING THE DIAGNOSTIC SOFTWARE 73 6.1.2 CHAIN FILE DIAGNOSTICS 6.1.3 RUNNING INDIVIDUAL TEST PROGRAMS 75 6.1.4 MEASUREMENT TOLERANCES 6.2 CHANNEL CARD TESTS 6.2.1 TRIMMING TESTS 6.2.2 FILTER TESTS 6.2.3 WAVEFORM MEMORY TESTS 6.2.4 MEMORY DUMP 6.2.5 ENVELOPE CONTROL TESTS 6.2.6 VOLUME CONTROL TESTS 6.2.7 TIMER TESTS 6.2.8 PITCH AND OCTAVE CONTROL 6.2.9 INTERRUPT FLAGS 6.3 MASTER CARD TESTS 6.3.1 TIMER TESTS 6.3.1.1 Timer Tests 6.3.1.2 Click Out...

6 diagnostic Software continued

Test no.1 P2 DMA MAP SWITCHING Test no.2 P2 DMA P1 UNIQUENESS DMA256 tests the automatic selection of special DMA mappings via the DMA claim lines which are input to the Q256 memory cards from all devices on the bus which use DMA (Floppy Disk Controller, Hard Disk Controller, General Interface card). P2 initializes map 29 with Block 2 of the test card mapped into K1 (logical area 4000 to 7FFF) as a 16K DMA buffer, and switches into map 29 to fill the buffer with its own page numbers. Then P2...

62 External Connections

4.6.8 Display module test (all segments on) 10 Digit write strobe 9,18, Key scan address and data to display modules 11-16 The Slave Keyboard Interface provides regulated power supplies to the CMI-11 switch modules in a slave keyboard and buffers the analog outputs of the switch modules before feeding them to the master keyboard controller. This section describes the operation of the cmi-14. The five slave key scan address lines from the master keyboard controller are fed straight through to...

63

V floating heater supply, and passes to the tube support card via P5 pins 2 and 3. R49 limits the current. To check the operation of the heater, look for the glow towards the back of tube neck. This combines the video and blanking signals and provides an output stage to drive the cathode. It also supplies and limits the necessary voltages to the rear of the tube Video output blanking '. '. Supplies signals

642 Mem256

MEM256 performs the bulk memory data and addressing tests, refresh and parity system tests. Purpose Checks both processors' abilities to write rapidly varying data throughout memory. In each test, the SELected blocks are mapped one at a time into 4000 to 7FFF and a semi-random data sequence written by either or both processors in an order as specified below. Each processor then checks its own data. Test no.1 PI ODD UP, P2 EVEN UP PI writes to all odd locations starting from 4001 and proceeds...

69

DAC Output swing, tests Ns2,3 0 to 5.6 0 to 1.88 0 to 2.6 Test N 4, Filter Distortion (VR2) Option R - channel card Revision Range 1-3 default 3- Reraove the short between TT10 and TT8 for this test. Second harmonic distortion in the CEM 3320 VCF (Revs 1 and 2 only) is minimised by adjusting the resonance control bias. The adjustment is made using a sine wave signal in the pass band of the filter, I.e. well below cutoff. A dummy sound Is played by the channel card at zero pitch, envelope and...

942 Audio Board Replacement 161

9.5 TOP COVER REMOVE REPLACE 9 6 SIDE COVER REMOVE REPLACE 9.7 BOTTOM COVER REMOVE REPLACE 9.8 DISK DRIVE REMOVE REPLACE 9.8.2 DISK DRIVE REPLACEMENT 9.9 FAN ASSEMBLY REMOVE REPLACE 9.10 CARD CAGE REMOVE REPLACE 9.10.1 CARD CAGE REMOVAL 9.10.2 CARD CAGE REPLACEMENT 9.11 REGULATED POWER SUPPLY ASSEMBLY REMOVE REPLACE 166. 9.11.1 REMOVAL 9.11.2 REPLACEMENT 9.12 MOTHERBOARD REMOVE REPLACE 9.12.1 REMOVAL 9.12.2 REPLACEMENT 9.13 TRANSFORMER END PLATE REMOVE REPLACE 1 69 9.13.1 REMOVAL 9.13.2...

Ad

6,8.3 Comprehensive Analog Test Chain test name ANALOG To check all analog functions of the CMI channel cards, master card, and audio card. This test is most conveniently used with the Analog Tester box connected to the rear panel of the CMI as labelled. Some cables need to be arranged slightly differently from normal. To make the changes, eject the disk(s), and turn power off first. (1) Keyboard Power cable, normally connected from the CMI to the Music Keyboard, should go to the analog tester....

Adclk

* A 2-way link option is provided on the CMI-25 motherboard whereby a Q096 64K memory card may be installed instead of the Q256, provided an old revision (Rev 5) master card Is used. The default linking on the motherboard connects pin 63A of a Rev 6 master card (PENB Input) to the Peripheral Enable output of the Q256. On an old master card, pin 63a is the Video Ram Enable (VRAMEN) output which connects via the non-default link, to the Graphics Controller VRAMEN input. The Q096 RAM card is not...

Baw62

This section provides a mixed blanking signal to the tube support card. The horizontal blanking signal extracted in the previous section is mixed with the treated vertical sync pulses taken from the vertical section. R11 and R12 also provide biasing for Q5 on the tube support card. The final mixed blanking signal passes to the tube support card via P4 pin 2. 9. VDU01 MAIN CIRCUIT CARD FUNCTIONAL DESCRIPTION (continued) 9.2 HORIZONTAL SECTION This section takes care of everything necessary for...

Byv96e

This section removes non-luminance information from the video signal during horizontal retrace. The horizontal blanking signal is extracted from the horizontal flyback pulses by D5, R9, R10 and R15. Each pulse turns Q4 on, which clamps the video signal via D1. The blanked video is then buffered by emitter follower Q3. R13 in series on the output corrects the impedance and protects the buffer. There is an optional link for selecting an external luminance signal (no sync). The selected signal...

C11

12 V supply to Q5, decoupled by C5. 7.5 V ref. to Q6, generated from 12 V by 85 V supply to cathode chain, decoupled Brightness control voltage, bypassed by 400 V (G2) supply via R33 and C11. Focus voltage via R24. R17, D4 and C7. by R21, C8 and C9. C10. Incorporated into the board layout is a ground ring around the tube connections. If any voltage goes dangerously high , the excess energy will arc over and be dissipated.

Cb2

-from keyswitch columns to keyswitch rows receives 9.6KHz clock CTS flag RTS flag keyboard data The keyboard receives + - 20 volts from the main computer's power supply along the same cable as the keyboard's data signals. These voltages are regulated to -12 +12 and +5 by the three terminal regulators located on the heat sink along the edge of the PCB. A 10 ohm 5 watt resistor is in series with the +20 volts and the 7812 +12 volt regulator to reduce power dissipation in the regulator. Audible...

Cd

14 1 C.M.I MAINFRAME DRAWING REF.DMC0001 REF.NO PART NO DESCRIPTION REMARKS 01 G0036 PANEL C.M.I TOP BEIGE 02 MC038 PANEL C.M.I REAR BEIGE 03 G0035 PANEL C.M.I SIDE BEIGE 04 G0050 PANEL C.M.I BOTTOM BEIGE 05 G0069 PANEL SUPPORT BASE 06 G0090 STRIP C.M.I FRONT B KG B K 07 G5054 DISK DRIVE LEFT (0) 08 G5055 DISK DRIVE RIGHT (1) 09 G0089 PANEL C.M.I FRONT 12- G0086 , C CAGE RAIL M BRD UPPER 13 G0033 PLATE DISK DRIVE TOP 14 G0034, PLATE DISK DRIVE BOTTOM 15 G0082 BRACKET CARD CAGE SUP TOP 16 G0081...

Chain Memdbgl

The chain calls the editor followed by the assembler to generate a new MEMDBG.CM on drive 1. Options in the chain include C - generate an assembly listing in the console screen P - print assembly listing on the line printer L - save assembly listing as the file MEMDBG.AL 1 CHAIN MEMDBG l C< return> to list to the console. The program consists of three sections A test executive, the menu, and the collection of test loops. Only the menu needs to be modified to include...

Cmitnt

With the CMI diagnostics disk in drive 0. It does not use the standard command interpreter but has its own commands to set up and run interrupt tests. Each Interrupt ha3 a predetermined priority such that if two or more interrupts arrived since the last interrupt service, the one with the highest priority gets serviced first. The level of an interrupt is a number indicating its priority such that the highest priority interrupts have a level of zero, and the others are arranged in ascending...

D10

*iM5 High voltage type (blue) IMS' High voltage type (blue) This is a +800 V supply derived from the winding between pins 6 arid 7, rectified by R50 and D10. The G2 -t-400 V supply is divided down by special high voltage resistors R54 and R56, passing to the tube support card via PS pin 7. The focus adjust pot is connected directly across the -t-800 V supply. The static focus voltage is mixed thru R57 with the dynamic focus signal at 031, the composite then passing to the tube support card via...

Dii

Replay sampled waveform C n Channel no. Test No.1 Display Routine The contents of the RAM buffer are moved to the specified channel card memory and the channel set running until < CNTRL-ESC> is typed. Monitor the waveform at TPS. It should be a low frequency triangle. This test allows a quicker check of sampled data than DBI. Both display routines are only necessary for debugging as the ADI test itself checks if sampled data is correct. Test No. 1 2 Jam and -Jr.jam Purpose Checks correct...

Fcxx

MIDI IRQ (CMI-08 only) 0 P SMPTE MIDI IRQ (CMI-28) 0 P Port select I P * The CMI-08 board only generates the MIDINT interrupt which is connected to the PI level 0 IRQ input on the Master card, along with the ACIA IRQ from the Q133. The CMI-28 board only generates the SMIDINT interrupt which is connected to the PI level 3 IRQ input on the Master card, along with the P1 IPI interrupt from the processor card. The B-side signals on pins 67-69 are duplicates of the corresponding signals on side A,...

Function

Available for peripherals ACIA registers Timer (6840) PIA registers, user and clock CPU 1 interrupt priOritiser CPU 2 interrupt prioritiser Shared 512 byte RAM Unique 256 byte RAM for each processor 4.2.1.2 Restart and Interrupt Vectors RAM space allocated uniquely to each processor provide independent interrupt vectoring. The vector locations are as follows ADDRESS (HEX) FFFE F FFFC D FFFA B FFF8 9 FFF6 7 FFF4 5 FFF2 3 FFFO 1 FFEE F FFEC D FFEA B FFE8 9 FFE6 7 FFE4 5 FFE2 3 FFEO 1

I

I ---------> sync 4 out 4.12.10 General Interface Support Card CMI-29 This circuit board contains the analog circuitry required for the I O for SMPTE and MIDI. There are 3 MIDI inputs (A, B & C) and 4 MIDI outputs (A, B, C & D). Provision has been made for a fourth MIDI input (D). The SMPTE input has a balanced line receiver. The signal is then filtered and converted to TTL compatible signals through the LM311 comparator. The SMPTE out signal is converted from a TTL to a balanced line...

Klt

Increase brightness control until picture background can be seen. 2. Adjust H. Phase control VR4 to centre picture horizontally within background raster. 1. Adjust H. Lin coil L2 to obtain optimum horizontal linearity at the start and end of the horizontal scan. 1. Turn V. Frequency control VR40 until picture starts rolling down the screen and the blanking bar is seen. 2. Slowly turn VR40 back so that bar rolls up and locks in. 3. Turn VR40 a few more degrees to ensure stable locking. 5.3.5...

Ymt

Note A reasonable knowledge of the technology involved and the dangers of working with high voltages is essential. This is where the signal enters the 7DTJ. The functions of this section arc Video input ' Video'' preamp DC restoration Mixed blanking Two outputs, video and mixed blanking are supplied to the tube support card. There is an external contrast control. The necessary blanking signals are derived from both the horizontal and vertical circuitry.

Info

The Various CPU functions is an 8 bit register in which each bit may be independently written to. This register is at location 6D, and it Is decoded by devices at 9B and 7A. When written to, the bit address is selected by the 3 least significant bits of the data byte. The state of data bit 3 determines whether the bit is set or cleared. The four functions provided per processor from this register are interprocessor interrupt hardware trace map switch select fast interrupt request where P is 0...

Memdbgc

The user i3 presented with a menu of tests indicating which parts of circuitry are exercised by each test. Simply type the number of the required test then answer the prompts for data such as which processor is to run the test, what data is to be used, what 16K memory block is to be written read etc. Once all data required for the test is obtained the test loop is entered immediately. The only thing left to do then watch the signals of Interest behave as the test loop requires. In general it is...

Ov

6.9.2 Channel Card Revs 1 and 2 (CEM Filter) 6.9.2 Channel Card Revs 1 and 2 (CEM Filter) Zero setting -3dB point (16Hz) expressed as binary fraction. Decimal point is placed between D5 and D6 inputs on DAC. (FILTA,14 setting not shown -3dB at 13.4kHz, -6dB at 19.3kHz) Zero setting -3dB point (16Hz) expressed as binary fraction. Decimal point is placed between D5 and D6 inputs on DAC. (FILTA,14 setting not shown -3dB at 13.4kHz, -6dB at 19.3kHz) 6.9.3 Series A Channel Card Rev 3 (SSM Tracking...

Pp

Balanced, 600 ohms input suitable for microphones. When the MIC LINE switch is in the MIC position, this irtput is fed to the Analog to Digital converter. Balanced, 600 ohm line level input. This Input is connected to the Analog to Digital converter when the MIC LINE switch is in the LINE position. Pin 2 INPUT'A. Amplitude of 1.4 volts P-P required for full scale conversion. Pin 3 INPUT B. Amplitude of 1.4 volts P-P required for full scale conversion. Direct input to the Analog to Digital...

Test Procedures 104

6.4.2 MEM256 6.4.3 MAP256 6.4.4 DMA256 6.4.5 MEMDBG 6.4.5.1 Use of MEMDBG 6.4.5.2 Adding Your Own Test Loops 114 6.5 Q133 CENTRAL PROCESSOR CONTROL MODULE 116 6.5.1 USER PERIPHERAL INTERFACE ADAPTER 116 6.5.2 SYSTEM TIMER 6.5.4 ACIA 6.6 Q219 LIGHTPEN GRAPHICS TEST 6.6.1 LGTST 6.6.2 LIGHTPEN TIMERS 6.6.3 LIGHTPEN PIA 6.6.4 PROCESSOR ACCESS SELECTION 6.6.5 LIGHTPEN DRAWING 6.6.6 VIDEO RAM TESTING 6.7 INTERRUPT TESTS 6.7.2 CMIINT COMMANDS 6.7.3 GENERAL PROCEDURE OF TESTS 124 6.7.4 ERROR MESSAGES...

Tp3

1 RTN Z Line in A 3 Line in B line in 50cket This test can also be performed using the Analog Tester box but the tester cannot gain access to the unfiltered channel output and uses the filtered output instead. This can indicate whether there is a major fault in the master filter but there is no point making accurate level measurements since the frequency responses of the channel card, master card, MIC or LINE input amplifiers and the tester itself are all superimposed. Set the tester to FILT...

Under No Circumstances Should Any Force Be Applied To The Neck Of The Tube

If the handling procedures for the tube prior to insertion in the chassis is such that there is a risk of personal injury as a consequence of accidental damage to the tube, then it is recommended that protective clothing should be worn, particularly eye shielding. Fig I.- . Lifting picture tube from edge-down position Fig I.- . Lifting picture tube from edge-down position Fig.2 - Lifting picture tube from face-down position Fig.3Lifting picture tube frpm face-up position Fig.2 - Lifting picture...

Vector

Restart NMI SWI1 Unused FIRQ SWI2 SWI3 Unused IRQ level IRQ level IRQ level IRQ level IRQ level IRQ level IRQ level IRQ level The Q133 contains two 2K ROMs that contain all the basic driver and initialization routines, such as loading the disk drivers and Q256's maprams. The monitor ROM occupies IK bytes from F000 to F3FF and may be accessed by either processor. Processor-unique workspace RAM is used by the monitor so both can be executing the monitor independently. Open 1-byte unit at address...

Vs

Unregulated power supply to music keyboard (also indirectly supplies alphanumeric keyboard). Pins 1,2 + 10V Return. Return (ground) for + 10V supply. Pins 3,4 + 10V Supply. Unregulated supply, +9 to +11 volts. Pin 5 -20V Supply. Unregulated supply, -18 to -22 volts. Pin 6 +20,-20 Return. Return (ground) for + and - 20 supplies. Pin 7 +20V Supply. Unregulated supply, +18 to +22 volts. Bi-directional serial data between mainframe and music keyboard, including busy flags in both directions. Power...

Wait

Initially, all interrupts are active, I.e., will be tested upon typing the RUN command. Tests can be activated or deactivated using the commands above. Each test begins with the processor interrupt mask set so that interrupts currently pending are ignored. The status registers associated with each active interrupt Is read in order to clear pending interrupts. These status registers generally contain a flag which indicates an interrupt has been generated and at this point the flag should be...

[

To understand the information below, three definitions are required Logical or Processor Space is the numerical range of addresses actually put out on the processor address buss. The logical address may also come from a DMA device such as the Floppy or Hard Disk controllers, MIDI card or Waveform Processor. Physical Space is the area of RAM which is actually accessed in response to the logical address. Mapping is the translation of any given logical address to any physical address. The Q256...

[Coption2

Test No.1 Light Pen Timer Read Write Latches Purpose 6840 timer preset latches can be written to and the counters read. Timers are put into preset state in which the counters always reflect the contents of the preset latches. Then each timer is write read tested with all numbers from 0 to FFFF. Each write read is a 16-bit transfer through the 8-bit buss. Test No. 2 Light Pen Timer Internal Clock Timeout Purpose Correct timeout from timers under internal clock. The internal clock is provided by...

441 Introduction

The floppy interface card interfaces the bit parallel serial buss of floppy disk drives to the C.M.I.'s interleaved parallel buss. The interface is a combination of device driver software, controlling disk data format arid initialization of data transfer parameters, and the hardware which carries out the transfers without processor intervention. Data is stored on the floppy disk itself on its magnetic coating, in concentric rings. In a standard, 8 inch floppy there are 77 such rings on each...

The Diskette In The Drive Under Test With

Tests can be run separately or in destructive non-destruct groups by typing as follows - DM,(0 or 1 or B) ,XT< returri> (Do all non-destruct tests) DD,(0 or 1 or B) ,X < return> (Do all destructive tests) ST < tests> ,(0 or 1 or B) ,X < return> where < tests> up to 10 test numbers separated by '-' The extended test option X accumulates error counts over a number of pass es . ESC key will abort test in progress. Typing 0S< return> will return the user to QDOS and reboot...

458 Video Memory Vram

The 16 kilobytes of VRAM is provided by eight 4116 16,384 bit dynamic MOS devices. The timing required for these devices is preset in the system timing signals. These signals are buffered and fed directly to the rams as BRAS* , BCAS* and BCA*. Memory refresh is done in the continuous access for screen refresh. Whenever the VRAM is directly accessed, the decoding at A2, 7D, 7E generates RENB, (active low). This disables the memory card in the 16K block used by VRAM and saves duplicating maps in...

Fairlight Lightpen Connector Gx20

The Light Pen is used to generate co-ordinate data from Hit and Touch signals coming from the light pen. These come onto the card via the lower 10-way connector. It is achieved by latching the bit, byte and line counters in the video chain when a touch and hit occur from the lightpen. The co-ordinates are then available to be read from the card by the processor. The light pen is activated by touching the insulated end of the pen, which generates a Touch signal. The interface can be configured...

19300

Note Fn indicates filter latch bit n Note Fn indicates filter latch bit n Test No.1 - Read-write 0 Purpose Tests memory read-write ability. First the waveform address counters are reset (A4,B3,B4) then the entire memory is written with zeros. The address count is automatically incremented after each write by having LOAD asserted and RUN not asserted. Memory is read back In the same way to verify data. Test No.2 - Read-write FF Purpose Tests memory read-write ability. Writes FF sequentially to...

Channel Outputs Is

The computer section of the C.M.I, houses all the digital control and sound generating hardware. It can he considered a stand-alone operational unit. With nothing connected to it it is possible to start up the system and bootstrap load the disks (BOOT the system). On power-up, EPROMS located on the C.P.U. Control Card Q-133 will control the Boot process. As soon as a disk is placed in the left-hand drive (Drive 0) a special sector known as the Boot Block is read into RAM and executed. The code...

Ctest name[Coption1Coption2

Where the Ctest name> is as described in each section. Options are of the form CO> n where < 0> is a single character and n is an integer. P n Repeat test command n times. Using C instead of an integer initiates continuous testing. N n Select test number n. There are usually several test commands with the same name. By default, all tests are executed sequentially but single tests or subsets of the available tests can be specified. For example N 1 Test no. 1 only ' N 1,3,5 Tests 1, 3 and...

Fairlight Cmi Repair

P2 tests all AIC memory location sequentially and using random test values. The 'FATAL AIC MEMORY ERROR' can be displayed by this phase of the RAM test. PI and the AIC's 6809 write to and read from alternate locations in the top half of AIC memory. PI and the AIC's 6809 write to and read from every 16th pair of bytesv A 100msec time delay is introduced between the read and write to test the AIC refresh The AIC moves it's test program to the top half of AIC memory and PI end the AIC's 6809 test...

4114 Dma Address Counters

Sixteen bit counter chain D1 to D4 Is used to provide the address for DMA transfers. The starting address for each disk transfer is established by writing the appropriate byte address to the address register then writing the address byte to the data register and then repeating for the other address byte. This causes the address to be preset into the DMA address counters by means of parallel-load strobe pulses STAL (low byte) and STAH (high byte). The incrementing of the DMA counters may be...

Cmi System Service Manual Music Keyboard Service Manual Alphanumeric Keyboard Service Manual Graphics Terminal

A 21-slot card cage houses a printed-circuit motherboard carrying edge connectors into which the C.M.I, circuit boards are inserted. The cards can be accessed by hinging down the front panel, and they can removed from the front of the unit without requiring the use of any tools. Cables from the front of each channel card connect to the audio board located inside the rear panel of the mainframe. This card supports a variety of audio functions, including balanced line drivers for the eight...

41 Q209 Dual 6809 Cpu Functional Description

4.1.1 INTRODUCTION 4.1.2 TIMING & MEMORY CONTROL LOGIC 4.1.2.1 Master Timing Signals 12 4.1.2.2 Dynamic Memory Timing Signals 12 4.1.2.3 Data, Address Buss Multiplexing 13 4.1.2.4 Interrupt Strobe Generation 4.1.2.5 Direct Memory A cess 13 4.1.3 CPU MEMORY SWITCHING, & VECTORS 4.1.3.1 Vector-Fetch Decoders 14 4.1.3.2 Processor System Control 4.1.3-3 Automatic Map Switching 4.1.3.4 Hardware Trace 15 4.1.3-5 Indivisable Instructions 16 4.1.3-6 Link Options 4.2 Q133 CPU CONTROL CARD...

4232 Eprom

Four kilobytes of U.V. erasable ROM are volt supply type used. These are 2716 2516, single 5 D4 F800-FBFF 2 Disk boot D5 F400-F7FF Both I O functions monitor 4.2.3.3 ACIA (Asynchronous Communications Interface Adapter) (refer to drawing Q133-02) 6551 ACIAs at E4, E5, E1 , E2, S3 are used to receive and transmit serial data. The BAUD rate is determined internally via internal dividers, from the baud-rate generator master 1.8432Mhz oscilator at D1. Interrupts generated by the ACIAs go to the...

3

Locate the circuit board onto its card cage rails. Component board should be facing towards the right. Clear the path of any connecting cables and slowing slide in the circuit board until it comes into contact with the motherboard edge connnctor. Locate the board into its polarising key on the motherboard. Now firmly push the board into the edge connector. Its ejectors should be in line with the adjacent ejectors. 4. Reconnect any cables that were removed in 9.2.1. 5. Replace the card cage...

7 Signal List Internal Connections 139

7.0 MOTHERBOARD SIGNAL LIST 7.1 COMMON SIGNALS BUSSED TO ALL SLOTS 140 7.2 SLOT 1 MASTER CARD CMI-02 7.3 SLOT 2 GENERAL INTERFACE CARD CMI-28 142 7.4 SLOT 3 TO 10 CHANNEL CARD CMI-01-A 7.5 SLOT 11 ANALOG INTERFACE CARD CMI-07 144 7.6 slot 12 64k system RAM QO96 (not used) 7.7 SLOT 13,14 256K SYSTEM RAM Q256 7.8 SLOT 15 FOUR PORT ACIA MODULE Q 14 7-9 SLOT 16 PROCESSOR CONTROL MODULE Q133 148 7.10 SLOT 17 CENTRAL PROCESSOR MODULE Q209 150 7.11 SLOT 18 LIGHTPEN GRAPHICS INTERFACE Q219 151 7.12...

8 Vdu03 Power Supply Unit

The power supply unit is located behind the front panel Light Pen cut-out. The unit consists of the power transformer, voltage selector switches and the regulated DC power supply card VDU03* The unit provides 24V and 12V for the Main Card VDU01 and 5V for the Light Pen. A multi-tapped primary power transformer is used. It has low magnetic leakage to prevent picture tube interference. The secondary output is connected via 3 pin connector to the Power Supply Card. The bridge rectifier DB1 and the...

Repair Of Raynet Board

Remove the Card Cage assembly, as Ln section 9*10. Remove all of the circuit board black rail guides by bending them until they snap out. Disconnect the DC power wiring loom going to the Regulated Power Supply assembly circuit board from the Transformer End Plate assembly. NOTE AND MARK ALL TERMINAL CONNECTIONS BEFORE THEY ARE UNPLUGGED FROM THE CIRCUIT CARD. Unscrew the six Philips-head screws and four counter-sunk screws securing the End Plate to the card cage support rails. Remove the...

431 Introduction

The q256 is a 256k x 9 bit dynamic RAM, organised as four blocks of 64k and mapped in 2 or 4K chunks. 32 different mappings from processor space to physical memory space may be set up. The mapping selected for any given cycle is automatically switched according to the current machine state. The machine state comprises which processor is on the buss, the user state system state output of the processor, and which DMA channel is active, if any. The ninth bit in the memory is a parity bit. Parity...

484 Power Supply

Raw D.C. supplies of approximately -t- and - 20 volts arrive at the card via connector PL4. When power is first applied, relay RLA is open and no power is fed to the regulator ICs. As capacitor C50 charges, the current through transistor Q8 increases until the voltage accross resistor R108 excedes .7 volts. Transistor Q7 then switches on, pulling the base of Q8 up to the supply, which causes relay RLA to close. Power Is then applied via RLA1 and RLA2 to the regulator ICs IC13 and IC14. The...

Power Supply

9.11.2 Regulated Power Supply Asssembly Replacement. 1. Position the Regulated Power Supply assembly back into its original position so that the terminal connectors removed in the above procedure can be reconnected. Reconnect all the terminals to the circuit board terminals, OBSERVING THE TERMINAL NUMBERING MARKED WHEN THE ASSEMBLY WAS REMOVED. 2. Push the Regulated Power Supply assembly into position and align the screws in the mounting rail to the holes in the black heatsink plate. 3. Refit...

GND fPIN

Sync Test Plug Circuit 3-pin Cannon Test No.1 Click Out Sync In 250Hz Time Purpose Checks click output and sync input circuits The first test clocks the Synch In timer timer 2 with a known frequency and checks its timeout against the software reference. During initialisation, timer 1 is checked to be working i.e. that it can be made to time out . It is then programmed for internal clock, and preset to run continuously at 250Hz with its output enabled. Timer 2 receives the sync input pulses and...

8

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 Pin 17 Pin 18 Pin 19 Pin 20 Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 26 MIDI out A. 5 volts. MIDI in A. SYNC out 1. MIDI out B. SYNC out 2. MIDI in B. SYNC out 3 MIDI out C. Digital Ground. MIDI in C. Digital Ground. MIDI out D. RESET START. MIDI in D. RUN STOP. SMPTE code in. Digital Ground. SMPTE code out. CLICK out SYNC out 4. CLICK in. CMI29 Analog Ground. CMI28 n c. CMI29 15 volts. CMI28 CMI29 -15 volts....

12 Schematic Diagrams 171

12.1 Q209 DUAL 6809 CPU 12.2 Q133 CPU CONTROL 12.3 Q256 256K MEMORY 12.4 QFC9 FLOPPY DISK CONTROLLER 12.5 Q219 LIGHTPEN GRAPHICS 12.6 CMI02 MASTER CARD 12.7 CMI01-A CHANNEL CARD 12.8 CMI04 AUDIO MODULE 12.9 QPSA POWER SUPPLY 12.10 Q137 FRONT PANEL 12.11 Q077 HARD DISK CONTROLLER 12.12 CMI28 GENERAL INTERFACE 12.13 CMI07 ANALOG INTERFACE 12.14 MAINFRAME WIRING DIAGRAM 13 EXPLODED VIEWS 13-1 TRANSFORMER' END PLATE 13-2 CARD CAGE ASSEMBLY

Graphics Video Memory Module 128 Kilobits

Fairlight Cmi Motorola Schematic

2.1 General Principles Refer to Figure 1 The C.M.I, is a complex special-purpose computer system which embraces many different hardware and software technologies. All processing and sound generation functions are performed by the Mainframe, while the Graphics Terminal and Keyboards serve as peripherals for operator interfacing. The mainframe is capable of operating quite autonomously, that is, it is not reliant on any external connections for proper functioning. Under certain conditions it is...

Aaaa

Fill memory from beginning address to end address User prompt for beginning address User prompt for end address Abort current command line, take no action Close current location, return to sequence start and open Relocate address AAAA by register R. R may be any of the CPU registers, the user relocation register, the monitor flag byte or the currently open location Relocate address AAAA by Relocation Register R Same as linefeed CTRL J except that no new line is taken, and neither the address...

O

Figure 3-1 Printed Circuit Board Option Block Location Under normal circumstances preventive maintenance is not required on the M2896. If severely dirty environments are encountered, an occasional cleaning of the drive may be performed 'to assure continued reliable performance. Only basic corrective maintenance is documented here. If it is determined that a disk drive requires more extensive repairs than are described in this section, return the unit to Fairlight Instruments for service. This...

Wd1791

The definitions of the control register bits are 0 DS0 drive select address bit 0 1 DS1 drive select address bit 1 2 enable interrupt active high 3 enable DMA address incrementing active low 4 DMA transfer direction l to disk The definitions of the control status bits are 7 device driver loading active low The extensive instruction set of the 1791 LSI can be obtained from the manufacturers data sheets for the 1791 - This device handles all data conversions between the disk drive and the C.M.I,...

32 Subsystem Checkout Without Substitution

System Interconnection Power System

In many cases the faulty sub-system will have to be identified using only commonly available test equipment. Minimum requirements are a multimeter for measuring volts D.C. and resistance, an oscilloscope, and the usual set of tools such as screw drivers, pliers, soldering iron, etc. The faulty sub-system can usually be isolated by the following tests Unplug keyboard input and try again. If system does not boot, fault is in mainframe. If it now boots, fault i3 in music keyboard, alpha keyboard...

Computer Musical Instrument

David Cilia

PDF format by Jean-BernardEmond amp David Cilia Version 1.0 f vrier 2001 Warning this Service Manual is only for Fairlight Computer Musical Instrument Model IIx For more information about other FAIRLIGHT products and company today CHI SYSTEM SERVICE MANUAL FAIRLIGHT INSTRUMENTS, FEBRUARY 1985 Revision 2.1 1. INTRODUCTION TO C.M.I. MAINFRAME