19300

Note Fn indicates filter latch bit n Note Fn indicates filter latch bit n Test No.1 - Read-write 0 Purpose Tests memory read-write ability. First the waveform address counters are reset (A4,B3,B4) then the entire memory is written with zeros. The address count is automatically incremented after each write by having LOAD asserted and RUN not asserted. Memory is read back In the same way to verify data. Test No.2 - Read-write FF Purpose Tests memory read-write ability. Writes FF sequentially to...

4

Note that the polarising keys in the edge connectors have to be running along the bottom of the card cage. The motherboard mounting screws will have to be positioned with its mounting holes. The CMI should be laying down on its bottom panel for this procedure. Align the motherboard over the screws and fit several nuts. Do not tighten the nuts at thi3 stage as the edge connectors have to be aligned to the circuit boards in the card cage. Stand the CMI on Its...

Channel Outputs Is

The computer section of the C.M.I, houses all the digital control and sound generating hardware. It can he considered a stand-alone operational unit. With nothing connected to it it is possible to start up the system and bootstrap load the disks (BOOT the system). On power-up, EPROMS located on the C.P.U. Control Card Q-133 will control the Boot process. As soon as a disk is placed in the left-hand drive (Drive 0) a special sector known as the Boot Block is read into RAM and executed. The code...

Ctest name[Coption1Coption2

Where the Ctest name> is as described in each section. Options are of the form CO> n where < 0> is a single character and n is an integer. P n Repeat test command n times. Using C instead of an integer initiates continuous testing. N n Select test number n. There are usually several test commands with the same name. By default, all tests are executed sequentially but single tests or subsets of the available tests can be specified. For example N 1 Test no. 1 only ' N 1,3,5 Tests 1, 3 and...

Fairlight Cmi Repair

P2 tests all AIC memory location sequentially and using random test values. The 'FATAL AIC MEMORY ERROR' can be displayed by this phase of the RAM test. PI and the AIC's 6809 write to and read from alternate locations in the top half of AIC memory. PI and the AIC's 6809 write to and read from every 16th pair of bytesv A 100msec time delay is introduced between the read and write to test the AIC refresh The AIC moves it's test program to the top half of AIC memory and PI end the AIC's 6809 test...

4114 Dma Address Counters

Sixteen bit counter chain D1 to D4 Is used to provide the address for DMA transfers. The starting address for each disk transfer is established by writing the appropriate byte address to the address register then writing the address byte to the data register and then repeating for the other address byte. This causes the address to be preset into the DMA address counters by means of parallel-load strobe pulses STAL (low byte) and STAH (high byte). The incrementing of the DMA counters may be...

Cmi System Service Manual Music Keyboard Service Manual Alphanumeric Keyboard Service Manual Graphics Terminal

A 21-slot card cage houses a printed-circuit motherboard carrying edge connectors into which the C.M.I, circuit boards are inserted. The cards can be accessed by hinging down the front panel, and they can removed from the front of the unit without requiring the use of any tools. Cables from the front of each channel card connect to the audio board located inside the rear panel of the mainframe. This card supports a variety of audio functions, including balanced line drivers for the eight...

41 Q209 Dual 6809 Cpu Functional Description

4.1.1 INTRODUCTION 4.1.2 TIMING & MEMORY CONTROL LOGIC 4.1.2.1 Master Timing Signals 12 4.1.2.2 Dynamic Memory Timing Signals 12 4.1.2.3 Data, Address Buss Multiplexing 13 4.1.2.4 Interrupt Strobe Generation 4.1.2.5 Direct Memory A cess 13 4.1.3 CPU MEMORY SWITCHING, & VECTORS 4.1.3.1 Vector-Fetch Decoders 14 4.1.3.2 Processor System Control 4.1.3-3 Automatic Map Switching 4.1.3.4 Hardware Trace 15 4.1.3-5 Indivisable Instructions 16 4.1.3-6 Link Options 4.2 Q133 CPU CONTROL CARD...

4232 Eprom

Four kilobytes of U.V. erasable ROM are volt supply type used. These are 2716 2516, single 5 D4 F800-FBFF 2 Disk boot D5 F400-F7FF Both I O functions monitor 4.2.3.3 ACIA (Asynchronous Communications Interface Adapter) (refer to drawing Q133-02) 6551 ACIAs at E4, E5, E1 , E2, S3 are used to receive and transmit serial data. The BAUD rate is determined internally via internal dividers, from the baud-rate generator master 1.8432Mhz oscilator at D1. Interrupts generated by the ACIAs go to the...

3

Locate the circuit board onto its card cage rails. Component board should be facing towards the right. Clear the path of any connecting cables and slowing slide in the circuit board until it comes into contact with the motherboard edge connnctor. Locate the board into its polarising key on the motherboard. Now firmly push the board into the edge connector. Its ejectors should be in line with the adjacent ejectors. 4. Reconnect any cables that were removed in 9.2.1. 5. Replace the card cage...

7 Signal List Internal Connections 139

7.0 MOTHERBOARD SIGNAL LIST 7.1 COMMON SIGNALS BUSSED TO ALL SLOTS 140 7.2 SLOT 1 MASTER CARD CMI-02 7.3 SLOT 2 GENERAL INTERFACE CARD CMI-28 142 7.4 SLOT 3 TO 10 CHANNEL CARD CMI-01-A 7.5 SLOT 11 ANALOG INTERFACE CARD CMI-07 144 7.6 slot 12 64k system RAM QO96 (not used) 7.7 SLOT 13,14 256K SYSTEM RAM Q256 7.8 SLOT 15 FOUR PORT ACIA MODULE Q 14 7-9 SLOT 16 PROCESSOR CONTROL MODULE Q133 148 7.10 SLOT 17 CENTRAL PROCESSOR MODULE Q209 150 7.11 SLOT 18 LIGHTPEN GRAPHICS INTERFACE Q219 151 7.12...

8 Vdu03 Power Supply Unit

The power supply unit is located behind the front panel Light Pen cut-out. The unit consists of the power transformer, voltage selector switches and the regulated DC power supply card VDU03* The unit provides 24V and 12V for the Main Card VDU01 and 5V for the Light Pen. A multi-tapped primary power transformer is used. It has low magnetic leakage to prevent picture tube interference. The secondary output is connected via 3 pin connector to the Power Supply Card. The bridge rectifier DB1 and the...

Repair Of Raynet Board

Remove the Card Cage assembly, as Ln section 9*10. Remove all of the circuit board black rail guides by bending them until they snap out. Disconnect the DC power wiring loom going to the Regulated Power Supply assembly circuit board from the Transformer End Plate assembly. NOTE AND MARK ALL TERMINAL CONNECTIONS BEFORE THEY ARE UNPLUGGED FROM THE CIRCUIT CARD. Unscrew the six Philips-head screws and four counter-sunk screws securing the End Plate to the card cage support rails. Remove the...

431 Introduction

The q256 is a 256k x 9 bit dynamic RAM, organised as four blocks of 64k and mapped in 2 or 4K chunks. 32 different mappings from processor space to physical memory space may be set up. The mapping selected for any given cycle is automatically switched according to the current machine state. The machine state comprises which processor is on the buss, the user state system state output of the processor, and which DMA channel is active, if any. The ninth bit in the memory is a parity bit. Parity...

484 Power Supply

Raw D.C. supplies of approximately -t- and - 20 volts arrive at the card via connector PL4. When power is first applied, relay RLA is open and no power is fed to the regulator ICs. As capacitor C50 charges, the current through transistor Q8 increases until the voltage accross resistor R108 excedes .7 volts. Transistor Q7 then switches on, pulling the base of Q8 up to the supply, which causes relay RLA to close. Power Is then applied via RLA1 and RLA2 to the regulator ICs IC13 and IC14. The...

GND fPIN

Sync Test Plug Circuit 3-pin Cannon Test No.1 Click Out Sync In 250Hz Time Purpose Checks click output and sync input circuits The first test clocks the Synch In timer timer 2 with a known frequency and checks its timeout against the software reference. During initialisation, timer 1 is checked to be working i.e. that it can be made to time out . It is then programmed for internal clock, and preset to run continuously at 250Hz with its output enabled. Timer 2 receives the sync input pulses and...

8

Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin 10 Pin 11 Pin 12 Pin 13 Pin 14 Pin 15 Pin 16 Pin 17 Pin 18 Pin 19 Pin 20 Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 26 MIDI out A. 5 volts. MIDI in A. SYNC out 1. MIDI out B. SYNC out 2. MIDI in B. SYNC out 3 MIDI out C. Digital Ground. MIDI in C. Digital Ground. MIDI out D. RESET START. MIDI in D. RUN STOP. SMPTE code in. Digital Ground. SMPTE code out. CLICK out SYNC out 4. CLICK in. CMI29 Analog Ground. CMI28 n c. CMI29 15 volts. CMI28 CMI29 -15 volts....

12 Schematic Diagrams 171

12.1 Q209 DUAL 6809 CPU 12.2 Q133 CPU CONTROL 12.3 Q256 256K MEMORY 12.4 QFC9 FLOPPY DISK CONTROLLER 12.5 Q219 LIGHTPEN GRAPHICS 12.6 CMI02 MASTER CARD 12.7 CMI01-A CHANNEL CARD 12.8 CMI04 AUDIO MODULE 12.9 QPSA POWER SUPPLY 12.10 Q137 FRONT PANEL 12.11 Q077 HARD DISK CONTROLLER 12.12 CMI28 GENERAL INTERFACE 12.13 CMI07 ANALOG INTERFACE 12.14 MAINFRAME WIRING DIAGRAM 13 EXPLODED VIEWS 13-1 TRANSFORMER' END PLATE 13-2 CARD CAGE ASSEMBLY

Graphics Video Memory Module 128 Kilobits

Fairlight Cmi Motorola Schematic

2.1 General Principles Refer to Figure 1 The C.M.I, is a complex special-purpose computer system which embraces many different hardware and software technologies. All processing and sound generation functions are performed by the Mainframe, while the Graphics Terminal and Keyboards serve as peripherals for operator interfacing. The mainframe is capable of operating quite autonomously, that is, it is not reliant on any external connections for proper functioning. Under certain conditions it is...

Aaaa

Fill memory from beginning address to end address User prompt for beginning address User prompt for end address Abort current command line, take no action Close current location, return to sequence start and open Relocate address AAAA by register R. R may be any of the CPU registers, the user relocation register, the monitor flag byte or the currently open location Relocate address AAAA by Relocation Register R Same as linefeed CTRL J except that no new line is taken, and neither the address...

10

Slide the Card Cage back into the mainframe. Refit the four screws at slot 20 end to secure the Card Cage to the disk drive mounting plates. Refit the right-angle brackets securing the left-hand side of the Card Cage to the black tube frame. Refit the two Allen head screws securing the left-hand side of the card cage. The cables removed from the circuit cards will have to be brought up from the bottom panel. This can be done by removing the appropriate circuit board rails from the bottom of the...

93 Vertical Section

Like the horizontal section, this provides everything necessary to maintain a sweep on the screen. It can be broken up into the following sections Sync conditioning Vertical oscillator Vertical IC decoupling Output feedback ' Res R137 This network cleans up the sync from either the sync separator or the optional sync input, which is then fed to TDA 2653 pin 2.

417 Adc Direct

Direct input to the Analog to Digital converter when the ADC DIRECT MIC LINE switch is in the ADC DIRECT position. Because this input is Direct Coupled, any D.C. offset on this input will result in a D.C. shift of a sound sample. Connector Type Cannon 3-pin. Pin 1 GROUND Pin 2 GROUND Pin 3 INPUT. Amplitude for full scale conversion is 10 volts P-P. Having isolated the faulty sub-assembly, service personnel should refer to the relevant service manual for further details about that item. Under...

Wd1791

The definitions of the control register bits are 0 DS0 drive select address bit 0 1 DS1 drive select address bit 1 2 enable interrupt active high 3 enable DMA address incrementing active low 4 DMA transfer direction l to disk The definitions of the control status bits are 7 device driver loading active low The extensive instruction set of the 1791 LSI can be obtained from the manufacturers data sheets for the 1791 - This device handles all data conversions between the disk drive and the C.M.I,...

32 Subsystem Checkout Without Substitution

System Interconnection Power System

In many cases the faulty sub-system will have to be identified using only commonly available test equipment. Minimum requirements are a multimeter for measuring volts D.C. and resistance, an oscilloscope, and the usual set of tools such as screw drivers, pliers, soldering iron, etc. The faulty sub-system can usually be isolated by the following tests Unplug keyboard input and try again. If system does not boot, fault is in mainframe. If it now boots, fault i3 in music keyboard, alpha keyboard...

Computer Musical Instrument

David Cilia

PDF format by Jean-BernardEmond amp David Cilia Version 1.0 f vrier 2001 Warning this Service Manual is only for Fairlight Computer Musical Instrument Model IIx For more information about other FAIRLIGHT products and company today CHI SYSTEM SERVICE MANUAL FAIRLIGHT INSTRUMENTS, FEBRUARY 1985 Revision 2.1 1. INTRODUCTION TO C.M.I. MAINFRAME