(refer to drawing Q077-04)
Sixteen bit counter chain D1 to D4 Is used to provide the address for DMA transfers. The starting address for each disk transfer is established by writing the appropriate byte address to the address register then writing the address byte to the data register and then repeating for the other address byte. This causes the address to be preset into the DMA address counters by means of parallel-load strobe pulses STAL (low byte) and STAH (high byte). The incrementing of the DMA counters may be inhibited under software control, so that disk data may be dumped directly into the data portholes on channel cards (CMI-01-A).
4.11.5 DMA BYTE TRANSFER COUNTERS (refer to drawing 0077-04)
Sixteen bit counter chain E5 to E8 is used to transfer the required number* of bytes to or from disk. It must be initialized with the inverse of the number of bytes to be transfered, (programmed as well as DMA transfers). Any number may be specified up to a maximum of 65,535 bytes. Only those bytes specified will be tranfered to memory on a disk read. This allows less than a sector to be read from disk, and saves the software overhead required to handle partial sector reads. The read takes place but the buss VMA signal goes inactive after the required number of bytes have been transfered, so disabling memory writes. The VMA disable signal_is_ generated from the ripple carry out on this counter chain, by buffering FINPS, (Finished Partial Sector). When a transfer occurs, the DMAC (Direct Memory Access Claim) line is generated so that the memory card swaps maps, allowing data to be dumped into memory currently not mapped into the processor's address space. This signal is generated by the components around flip-flop CIO.
4.11.6 DATA BUFFERS
(refer to drawing Q077-02)
Data is propagated from the system data bus via latch B4 which hold the data across the processor 1 phase. This latched data also becomes the DATA FROM BUS via buffer B5, to the controller card.
Data written to the system control register is:latched by C4. This controls such functions as controller reset.
4.11.7 address decoding, controller :
Address range $FC5A-$FC5B is decoded by gates 31, CI, F4,F1 and latched by F3.
Address $FC5A is used to enable the internal data buss to read and write to controller functions. The least significant 3 address bits written to latch'. B7 are propogated down the cable to the controller card
Address $FC5B data is latched by B7 and with the access to FCEO generates the internal chip selects and read/write strobes through E5. The least significant 3 address bits written to latch B7 are propogated down the cable to the controller card.
Buffers C9, C8, are used to interface the Q077 to the controller 50-way cable. All cable signals are terminated in 220ohm/330ohm terminating networks.
The Interrupt Request from the controller is gated with the Interrupt Enable to provide an open-collector interrupt signal for the system IRQ on buss pin 63A.
4.11.8 DMA LOGIC
(refer to drawing Q077-03)
Data requests from the controller or Device Driver rom loading are synchronised with Processor 2 Phase 2 using flip-flops B9 and A10. This sets up a DMA request to the processor (RDMA).
Flip-flop B9 only allows a DMA cycle to occur every second Processor cycle (the floppy drive can not transfer at that rate but this is a system constraint on other DMA devices in the DMA daisy chain). _
The DMA daisy chain is controlled by ENL and EDLRespectively these stand for, Enable Next Level and Enable Dma Level. When EDL is active, a DMA request may be requested by the highest priority device. The ENL signal informs the next device in the daisy chain that it may make a request if higher priority devices have not.
Depending on which function has been requested (Reset, Read, write) the required DTB (Data to Bus), and ATB (Address to Bus) signals are issued.
During a D.M.A. cycle, the address to the controller board is set to $0 by the AND gates at BIO. This selects the FIFO In the controller card which is the origin (for a read) or destination (for a write) for the data in the transfer.
4.11.9 CONTROL REGISTER
The control register contains the controller reset, Interrupt enable and increment DMA address enable. This register is the latch at C4.
4.11.10 DEVICE DRIVER ROM
(refer to drawing Q077-05)
The disk controller software may be placed in a 2K or 4K EPROM on the controller card. This EPROM is not in the processors directly addressable memory. It is executed by reading the software into RAM. This is done by DMA. The EPROM is copied into RAM as if reading a disk, except much faster.
The least significant DMA counter lines are used as addresses on the EPROM, so the EPROM can only be loaded into memory on 2k or 4k boundaries. The flip-flop C10 and gates in D9 and B8 produce a DMA write to memory request that is terminated after the byte counter times out.
The General Interface Card (CMI 28)' is an optional card for the; Fairlight CMI Series IIX. Please note that for use in the Series IIX machines a CMl-25 rev-3 motherboard is required (or equivalently modified old motherboard). The General Interface Card is designed to handle reading and generating of SMPTE code and to control four MIDI ports as well as controlling the CLICK feature. Because its main purpose is for SMPTE and MIDI It is often referred to as the SMIDI Card. In the Series IIX machines the card is plugged into the second slot on the left between the Master Card and a Channel Card.
The SMIDI card is connected to the General Interface Support Card, the CMI-29 via a 26-way cable. This card is housed in a box bolted to the back of the CMI. This support unit has the opto-couplers, and open collector buffers for receiving and transmitting MIDI as well as the analog circuitry for reading and generating SMPTE code to tape.
The SMIDI card in general is a microcomputer system with a Motorola 68000 microprocessor, either 8k or 16k words of ROM and either 8k or 32k words of static RAM. It is possible to extend this to 64k words. It has a DMA interface to the CMI with the capability of DMAing to either P1 or P2. In Series IIX machines the DMA is only on P1. The card has 4 ACIA's (68B50) for-the 4 MIDI ports, two 68B40 Programmable Timer Modules as well as associated circuitry for reading and generating SMPTE code and click/sync in and multiple syncs out.
There are four 28-pin sockets for ROM and static RAM. The minimum configuration is 8k words of ROM (2 x 2764) and 8k words of static RAM (2 x 6264). The ROM can be configured for 16k words by breaking the link (LK1) between pin 27 of the ROM and +5v and join the link LK1 to A15 from the processor and plugging in the appropriate two 27128'3. Similarly the RAM can be arranged to accommodate 32k static RAM chips (e.g., MK4856 pseudo-statics) by breaking the links LK2 and LK3 to +5v and connecting A14 and A15 to pins 26 and 1 of the RAM chips (via LK3 and LK2), respectively. Further, there is an option for 64k words of RAM; by soldering two 32k RAM chips on top of each other except for pin-20, the chip select, which should be connected to the pads provided from the select circuitry, the AND gates (D12). All these memory expansions will depend on the availability of these chips.
NOTE; when plugging in the ROM's, they should be labelled 'odd' and 'even'. The even one should be plugged into E5,6 (near the 68000) and the odd one into E8 (between the RAM chips).
Memory addressing: ROM starts at $000000 and RAM starts at $080000.
4.12.3 68000/6809 DMA Bus Interface (Refer to Drawing CMI-28 rev 2 page 4.)
Communication between the 68000 processor and the 6809 CPU is achieved by DMA (Direct Memory Access) on the system bus. The 68000 waits until no higher priority device is occupying the bus and then either 6809 CP1 or P2) is temporarily hung while the 68000 executes a normal bus cycle writing to or reading from memory or a peripheral on the bus. In this manner the entire 64K address space of each 6809 processor appears as a small slice of the 16 megabyte address space of the 68000. Software then defines various protocols for the different processors to pass messages and data to one another by simply placing them in system memory.-
The DMA interface provided on the 68000 SMPTE/MIDI Card Is a very flexible one. It automatically handles either 8 or 16-bit data transfers (doing double cycles across the 8-bit CMI bus in the latter case) and can do so on either PI or P2 cycles, selecting any desired memory mapping which has been set up on the Q256 memory card.
DMA is initiated by the 68000 when it accesses any address in the range $040000 to $05FFFF. These addresses are decoded by the LS259 (E12) on drawing CMI-28-1/7 and result in the CMI signal being asserted (low). Since the rest of the interface circuitry is not activated yet, PACK (to be explained later) will be low and a low will be presented at the data input of flip flop C12(a) whose function is to synchronise the transfer with the CMI bus.
Address line A16 is used to select which 6809 processor's bus cycle(s) are to be used for the transfer. The timing signals for both processors are Input to LS241 buffer A7 which is wired as a muliplexer:-
If A16 is low, P2«52 is enabled through to become Pc52, ADD2 becomes PADD and so on. If A16 is high, Pi's timing signals are enabled instead.
By this means, the address range specified above is split in two: from $040000 to $04FFFF the transfer automatically occurs on P2 bus cycles, while from $050000 to $05FFFF it occurs on P1 cycles. Refer to the 6809 CPU documentation for more information on the interleaved P1/P2 CMI bus cycles.
Thus at the beginning of the data cycle of whichever processor is selected, the PzS2 signal clocks the LS74, recording the fact that a DMA cycle is required.
All DMA devices are interconnected on the motherboard in a "daisy chain". Each device is assigned a given priority in the chain and must wait until no higher priority device is already using the bus. The 6809 CPU is the always the last device in the chain. There are two separate daisy chains in the CMI system, one for each 6809 CPU. Since the 68000 SMIDI card can perform DMA on either CPU's cycles, it is a member of both chains. ETL1, ENL1 and RDMA1 are the chain signals for PI, ETL2, ENL2, RDMA2 are for P2. Which set are used is again selected by the state of A16 at the time of transfer.
The selected ETL (Enable This Level) signal is low when no higher priority device is occupying the bus. After the CMI signal has been latched, nothing happens until this signal is low, whereupon the RDMA (Request DMA) is driven low through the selected LS12 gate. Any DMA device pulls this open collector line low to to request bus access to the CPU. At the same time, the_selected ENL (Enable Next Level) signal is inhibited. Normally, the low on ETL comes in and goes out again on ENL to indicate to lower priority devices that the bus is available but when the 68000 requires a transfer ENL is held high to hold up the lower devices.
The CPU acknowledges that it will hang and release the bus for the next cycle by asserting ACK1 or ACK2; the_selected ACK signal becomes PACK. When a request has been generated (C12(a) Q hi) and this level is enabled (ENL lo), the rising edge of PACK clocks a low into flip flop B11(a) to generate DCYCLE. This signal indicates that the next bus cycle is definitely going to be a 68000 DMA transfer and remains asserted until the end of the address phase of the actual DMA cycle.
the other half (b) of B11 is also clocked by PACK to generate the PT or P2 DMAC (DMA Claim) signal as selected by A16. This signal goes to the Q256 RAM card to select the memory mapping which has been set up specifically for the 68000. In this way the 68000 may have access to part or all of the same physical memory space as the 6809 CPU or it may have access to an entirely different part of physical memory as required by software. The DMAC signal is asserted during the data cycle preceding the actual transfer. __
The address phase of the DMA cycle is indicated when ATB (Address To Bus) is asserted by the LS10 B10. At this time the lower 15 bit3 of the 68000 address bus are enabled on to the CMI bus through the two LS244's A2 and A3 to select the required location within the 6809 address space. VMA is driven high through LS125 B1 to indicate a Valid Memory Address and the 68000 R/W line is driven through the same buffer to indicate a read or write cycle. When the 68000 perforins 8-bit memory accesses, the UDS and LDS signals (upper and lower address strobes) Indicate whether an even or odd address is being accessed. The sense of these signals are clocked into JK flip flop H12 at the beginning of DCYCLE to generate HIBYTE and L0BYTE. The latter signal becomes the least significant address line driven onto MAO through A3.
In the case of 16-bit accesses, the hardware automatically requests two successive DMA accesses across the 8-bit CMI bus. Both UDS and LDS are asserted so that the JK outputs HIBYTE and L0BYTE simply toggle on each access. It does not matter which byte transfers first and in fact this depends on the initial state of N6. L0BYTE directs the data to or from the odd or even address and both signals control whether the higher or lower 8 data lines are directed to the data bus.
The data bus interface consists of Schmitt bidirectional bus transceiver LS640 A6 and bidirectional driver/latches C5 and C6 (LS646s). The data phase of the DMA transfer is indicated by the assertion of DTB (Data To Bus) at the rising edge of BRA when a DMA cycle Is in progress. This is performed by flip flop' MN4. DTB enables the bus transceiver a6 and the direction is determined by the 68000 R/W signal.
If the 68000 is writing to the CMI bus, C5 or C6 simply act as buffers to transfer the_high or low 68000 data signals (PD0-15) through to A6. HIBYTE or L0BYTE plus CMI being asserted will drive the G input of the appropriate LS646 for the duration of the DMA cycle (LS02 and LS32 gates M2 and M1).
When the 68000 reads from the CMI bus, C5 or c6 must latch the data in from the bus to hold it until the 68000 terminates its own cycle and latches the data internally, about 50nS after the end of the DMA cycle. 100nS before the end of the data phase, the CMI timing signal CAS goes low, resulting in a rising edge on BCAS. Data from memory is guaranteed to be valid at this time. B10 generates the LDATA (Latch Data) signal which is ANDed with either HIBYTE or LOBYTE to latch the data coming into the A side of C5 or C6. The output of the latch (B side of the selected LS646) is driven onto the PD lines until the 68000 completes its cycle and negates CMI.
Termination of the transfer after single or double DMA cycles is controlled by the two flip flops in LS74 C10:
In the single (8-bit) transfer case, either UPS or LDS will be low. This will cause the LS10 A10 to output a high, and DTACK2 will be generated a3 soon as LDATA occurs. The 68000 will then terminate its cycle immediately, after only one DMA cycle.
In the double DMA cycle (16-bit) case, both UDS and LDS are high so DTACK2 will not be generated until the first flip flop In C10 Is set. Initially this flip flop is reset. At the first LDATA pulse a high is clocked in but DTACK2 is not generated because of the propagation delay through to the next flip flop. Since DTACK2 is not asserted, the 68000 still waits with address and address/data strobes asserted. If writing, the data remains asserted by the 68000 but both address and data are removed from the CMI bus when ATB and DTB
are negated respectively._If reading, the first byte read in is latched and held by C5 or C6. Since CMI will still be asserted and PACK will have been negated, the whole process of waiting for daisy chain priority and DMA requesting begins again in order to perform a second DMA cycle. The second cycle can be held up indefinitely by higher priority devices using the bus after the first cycle. When the second LDATA edge comes along the high on the LS10 output is clocked into the second C10 flip flop and DTACK2 is asserted. On the next falling edge of PCLK, the 58000 recognises that DTACK has been asserted. On the second falling edge of PCLK the data is latched internally for a read, and the address and strobes are released. The low on BAS resets the flip flops at C10.
If the timing circuitry of the DMA interface is faulty, the most likely result is that DTACK2 will never be generated and the 68000 will simply hang which makes debugging easy. In this case, check first that the address decoding is" generating CMI, then that the daisy chain signals are present. Then look for an 800nS pulse on DCYCLE, indicating that DMA cycles are actually ocurring. Continue through to the ATB, DTB and LDATA signals, checking not only that they are generated but also that they get to their respective destinations in the circuitry.
If the DMA cycles are being synchronised and timed correctly check that the address buffers and data buffer/latches are being enabled and clocked at the correct times.
If all timing circuitry is correct, the last possibilty is data or address bus shorts, open circuits or faulty drivers. Special test ROMs are available Which cause the 68000 to repetitively copy bytes and words from one location to another in CMI memory. The 6809 monitor can then be used to deduce which data Or addresses cause problems.
4.12.5 SMPTE/MIDI Card peripheral Circuits
There are four different peripheral circuits on the SMIDI card.: Firstly, there are the four ACIA's (G7-11) which are the MIDI ports A,B,C, and D. Then there is the Timer (bottom rev.2 G5,6) which is used: in conduction with the SMPTE read and generate circuits (which are the other two circuits) as well as the Click In and Out.
The ACIA'S and Timers work from an 8-bit data bus with (asynchronous) interfacing circuitry. They are driven also by the E (enable) signal from the 68000. The frequency of this clock is one-tenth of the 68000 clock (10MHz) with a 60/40 duty cycle (6 clocks high, 4 clocks low)
Initially the flip-flops (F2) are cleared causing a high DTACK3 output setting the LS646 transceiver (G4) into the transparent mode. The direction of data flow is determined by the R/W line with the 10: selected. Without 10 line selected it appears in write mode. The:peripheral is selected by the LS138 enabled by the CS' signal. The first flip-flop F2(a) is clocked on the first falling edge of E with the:10 select and the data strobe high (ie either LDS Or UPS low). The Q output of F2(a) is applied to the NAND gate (G3)> asserting CS*. Selecting the peripheral at this time ensures that the peripheral has adequate address setup time.
On the next falling edge of E, the Q output of F2(b) is clocked low asserting DTACK3 and latching data in the transceiver (G4). The asserted DTACK3 signal deselects the peripheral by causing CS' to go high. Flip-flop F2(a) is cleared by 10 going low when the access terminates. Clearing flip-flop F2(a) also initializes the interface circuitry for the next access .
The ACIA's are selected by E10 and appear at addresses; $60020, $60030, $60040 and $60050. They share a common interrupt level - level 3- Their transmit and receive data lines are wired to the 26-way connector to be connected to the MIDI drivers and opto-coupler receivers.
The programmable timer (G5,6) appears at the general address $60000, and has an interrupt level-2 to the 68000.
RAM is fast enough (150ns) to not need a delay on the DTACK line, so that when RAM is selected DTACK Is also enabled. Not so with ROM, a delay is needed and is provided by the LS161 counter (F1) which delays the enabling of the DTACK line by 12 processor clock cycles.
The 68000 has seven levels of interrupts. The priority for the interrupts is made by hardware through the 74LS148 ic (C2). The lowest level Interrupt (INT1) and the NMI (INT7) are enabled and cleared by the CMI through the control port (B4). INT2 is for the 68B40 Timer, INT3 is for the ACIA's. INT4 is for reading a SMPTE 'one' and INT5 for a SMPTE 'zero' and are cleared by addressing location SMPTEWR on i.e. E10 (LS138). INT6 is for SMPTE generation and is cleared by writing to the shift registers (C7,C8), i.e. by signal SMPTERD.
An oscillator (3.84MHz) is divided by 10 (G2,G1) to provide a standard for generating the 3 different rates of SMPTE code (24, 25 and 30 frames per second). All three are denominators of 384,000. Further division, depending on the frame rate selected, is done by the Timer (G5,6) giving the signal CLK2, which is the bit rate for a SMPTE 'one' (ie 160 bits per frame). This is in turn divided by 2 (C11) giving CLK1 which is the bit rate for a SMPTE 'zero' (ie 80 bits per frame). When a SMPTE word is ready it is written to the Parallel-In-Serial-Out registers (C7,c8)at address $60070 (through B9,B8 and B7). When this writing takes place the Interrupt INT6 if it has been asserted is now cleared. The data in the shift registers (C7,C8) is clocked out by CLK1, a 4-bit counter (D11) is also clocked which causes the interrupt on level-6 (INT6) when it reaches its terminal count of 16. Now, if a 'zero' is shifted out from C8 the flip-flop C11 is toggled at the rate determined by CLK2, but if a 'one' is shifted out from C8 the flip-flop C11 is toggled at the CLK1 rate. Thus, the word stored on the shift registers is outputted in SMPTE form.
4.12.8 SMPTE Reading Circuitry (Refer to Timing Diagram)
SMPTE code coming from tape, being converted to TTL signal levels by the CMI-29 board, is received by the CMI-28 through pin 17 of the 26-way connector. The circuitry consisting of the EXOR gates .(C1) and the resistor-capacitor combination creating a pulse (at pin 6 of CI) for every up or down transition of the incoming signal.
The required output from this SMPTE data separator is to have one interrupt occur for every SMPTE 'one' read and another interrupt for every SMPTE 'zero' read. This process can be followed through with the timing diagrams. The 68B40 timer is set, according to the frame rate of the SMPTE being read, to 3/4 of the time for one bit cell. The circuit then detects whether there has been a transition in that time or not. If there has been a transistion then a 'one' is read, if no transition occurred then a 'zero' is read.
The SMIDI card also takes care of some of the sync-ing functions of the system. On revisions 1 (modified) and 2 of the CMI-28 SIDI board there are two 68B40 programmable timers (each with 3 timers inside), one wired on top of another. The input clock of 3rd timer in the bottom 68B40 (timer a) is wired to the Click/Sync input socket on the support box mounted to the rear panel of the mainframe. The output of this timer is fed into the inputs of the three timers in the top i.e. (timer b) providing a cascaded timer system. These four outputs are fed to the CMI-29 in the support box, to a 5-pin DIN socket via open-collector buffers.
Was this article helpful?
Read how to maintain and repair any desktop and laptop computer. This Ebook has articles with photos and videos that show detailed step by step pc repair and maintenance procedures. There are many links to online videos that explain how you can build, maintain, speed up, clean, and repair your computer yourself. Put the money that you were going to pay the PC Tech in your own pocket.