441 Introduction

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The floppy interface card interfaces the bit parallel/serial buss of floppy disk drives to the C.M.I.'s interleaved parallel buss. The interface:is a combination of device driver software, controlling disk data format arid initialization of data transfer parameters, and the hardware which carries out the transfers without processor intervention.

Data is stored on the floppy disk itself on its magnetic coating, in concentric rings. In a standard, 8 inch floppy there are 77 such rings on each side called tracks. Tracks are divided into data blocks called sectors. Sectors in Fairlight disk formats are either 128 or 256 bytes per sector, depending on operating system being used. The smallest amount of data that can be read to or from a disk is one sector. Sectors on a disk may be randomly accessed.

Track 0 is outermost. The controller automatically restores to this track on power on, and on reaching track 0, signals the controller by a mechanical switch generated signal. All head movement is relative to this reset state.

Floppy drives transfer data serially. They: also have parallel control lines to control drive number selection, head stepping direction, head load, disk write and disk write enable. The head of the drive must be lowered to the disk surface before a transfer may take place, this is operation referred to as "head load". Index pulses are generated by the drive so that the controller knows the location of the rotating disk. This pulse occurs once per revolution, 30 the start of tracks can be determined by the controller. Also, the controller generates pulses that are used to step the head in and out to position it over the required track.

The Floppy Disk Controller/Formatter uses the WD1791 controller LSI. It is software Selectable to double density, double sided in addition to single density, 3ingle sided. It is designed to work with CPU #2's, transferring data to and from memory by DMA on Processor 2. The processor is not involved with transferring data to and from the disk. Once a data transfer is set up the processor may continue processing other tasks until the interrupt for "command complete" is issued by the controller.

4.4.1.1 Address Map

(refer to drawing QFC9-01)

The controller is accessed through two locations, in a memory map which enables access to peripherals. An address register is set up to point to the required controller register. All data is read or written through a single data register.

ADDRESS (HEX) READ WRITE

FCEO data data

FCE1 status register address register

The 7 controller registers are ...

00 control register

02 DMA address (low byte)

04 DMA address (high byte)

06 byte count to read/write (low byte, inverted)

08 byte count to read/write (high byte, inverted)

OA command location to load device driver ROM into RAM

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