458 Video Memory Vram

(refer to drawing Q219-06)

The 16 kilobytes of VRAM is provided by eight 4116 16,384 bit dynamic MOS devices. The timing required for these devices is preset in the system timing signals. These signals are buffered and fed directly to the rams as BRAS* , BCAS* and BCA*. Memory refresh is done in the continuous access for screen : refresh.

Whenever the VRAM is directly accessed, the decoding at A2, 7D, 7E generates RENB, (active low). This disables the memory card in the 16K block used by VRAM and saves duplicating maps in the Q256: ram card.

.4,6*3 Introduction

The CMI02 Master Card performs a variety of functions including control of the eight channel cards, analog to digital conversion for sound sampling, and timer functions for sequencer and Music Composition Language. It occupies the first slot from the left in the card cage of the C.M.I. Mainframe.

This card occupies 64 bytes of processor address space. It can be accessed by either processor. The address map is as follows:

ADDRESS (Hex) FUNCTION

E000-E01F CHANNEL CARD REGISTERS

E020 CHANNEL MASK DATA REGISTER (P.I.A)

E021 CHANNEL MASK CONTROL REGISTER (P.I.A.)

E022 MASTER TUNING DATA REGISTER (P.I.A.)

E023 MASTER TUNING CONTROL REGISTER (P.I.A.)

E024 A.D.C. DATA HIGH BYTE

E025 A.D.C. DATA LOW BYTE

E026 HALT PROCESSOR 2

E027 UN-HALT PROCESSOR 2

E028 LEVEL CONTROL DATA REGISTER (P.I.A.)

E029 LEVEL CONTROL CONTROL REGISTER (P.I.A.)

E02A FILTER CONTROL DATA REGISTER (P.I.A.)

E02B FILTER CONTROL CONTROL REGISTER (P.I.A.)

E030 P.I.C.U. ENABLE CURRENT STATUS

E031 INTERRUPT PROCESSOR 1

E032 CLEAR PROCESSOR 1 INTERRUPT

E033 INTERRUPT PROCESSOR 2

E034 CLEAR PROCESSOR 2 INTERRUPT

E038-E03F TIMER REGISTERS (6840)

4.6.1 ADDRESS DECODING, CHANNEL SELECTION, MASTER TUNING REGISTER (Refer to Drawing CMI02-01)

4.6.1.1 Address Decoding

Addresses in the range E000-E03F are decoded by NAND gate A1. Once addressed, the SEL (Select) signal is latched by D-type flip-flop C1. Channel card addresses in the range E000-E01F are decoded by NOR gate C2 to produce CHSEL (Channel Select).

4.6.1.2 Channel Selection

All eight channels occupy the same address space and channel selection is achieved by establishing a mask of desired channels in the B side of P.I.A. BC9 (Channel Mask). NAND gates A10 and B10 enable one or more channels when a WRITE to- a channel card address is performed. It is not possible to read from more than one channel at a time without buss contention, so circuitry is provided to protect against crashes which may result from a software bug which causes inadvertant reading from multiple channels. ROM A9 is programmed to generate a logic zero if more than one bit is set in the channel mask. If a READ is attempted under these conditions, the CHSEL is inhibited.

4.6.1.3 Master Tuning Register

The B side of P.I.A. BC9 is configured as outputs, the data written to it being used as Master Tuning control (MT0-MT7) by the Master Pitch generator (Sheet 2).

4.6.2 INTERRUPT CONTROL, MASTER OSCILLATOR, MEMORY CONTROL (Refer to Drawing CMI02-02)

4.6.2.1 Interrupt Control

The eight channel cards generate Processor 1 interrupts which occupy the eight interrupt levels supported by the C.P.U. Control Card Q133. To support the remaining interrupts, a second P.I.C.U. (Programmable Interrupt Control Unit) is provided on the Master Card. It is cascaded with the one on the Q133 card.

The P.I.C.U. C8 normally provides the three highest priority interrupts to Processor 1. These are, IRQSYN from the keyboard A.C.I.A., TIM1N1 from the 6840 timer, and interprocessor interrupts. The current interrupt priority level is written to the P.I.C.U. by a WRITE to E030 (hex). If an interrupt of a higher priority arrives, the T7IT output of the P.I.C.U. will be asserted (low), setting the flip-flop formed by gates A10, B2 and generating a Processor 1 Interrupt Request (IRQ1). The level of the interrupt is presented to the Interrupt Address Buss IA01-IA21. This address is used as bits 1 to 4 of the memory address when fetching the interrupt vector.

The interrupt latch is cleared when a hew interrupt status is written to the P.I.C.U.

4.6.2.2 Master Oscillator

Transistor Q1 and crystal Y1 form a 34.29 MHz oscillator from which the channel card pitch reference is derived. Flip-flop E10 divides the output of the oscillator by 2 to provide a symmetrical square wave at 17 MHz. This is fed to rate multipliers C10 and D10, which give a small range of frequency control, as determined by the data from the Master Pitch register (sheet 1). The output of these rate multipliers is fed to all channel cards via buffer A7»

4.6.2.3 Memory Control

Counters E8 and d8 are clocked by the 17 MHz signal from the crystal oscillator and their output addresses timing ROM B8. This ROM generates the timing signals required by the Waveform RAM on the Channel Cards. They are SREF (Refresh), SHIT (Row Address), SRAS (Row Address Strobe), SCAS (Column Address Strobe). The outputs of the ROM are latched by quad flip-flop B7 and buffered onto the buss by A7-

4.6.3 Analog to Digital Converter (Refer to Drawing CMI02-03)

The Analog to Digital converter is an AD571 (D7), of 10-bit accuracy. The sample rate is determined by the frequency set up by the Channel Card in the Channel 1 position of the Mainframe. This clock: arrives at the Master Card edge connector pin 44. ADM (A-D Mode) is normally low, enabling the ADCLK (A-D Clock) through to one-shot D2. This one-shot generates the 2 uS pulse required by the AD571 to start a conversion cycle.

When waiting for a conversion cycle, Processor 1 halts itself by accessing E026 (hex). This generates a tTSFT strobe, CLEARing flip-flop D3 which causes HCT (Halt) to go low.

When the conversion is complete (approximately 30 microseconds later) the UK" (Data Ready) output of the AD571 goes low, forcing the output of NOR gate D9 High, clocking the data latches C5 and C7» which capture the data ready for reading by the processor. At the 3ame time as the conversion is completed, flip-flop D3 is clocked, setting it. The t? output is forced LOW again, removing the HALT condition from Processor 1 and allowing it to run again and read the A-D data. If Processor 1 is held halted for more than 100 mS, one-shot D2 times out, allowing it to run again. This is to protect against system hang-up in the event of an A-D failure.

The audio signal arrives at the Master Card at pin 9 of the 10-way ribbon cable plugged into the front of the card. Sample-and-hold E9 is gated by the W (Data Ready) signal from the DAC to ensure that the signal input to the DAC remains constant while a conversion is in progress.

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