34 Detailed Circuit Descriptions

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Note:

Capacitors of 0 pF, and resistors of 100 MQ shown in circuit diagrams are not placed on the PCA. They are drawn in the circuit diagrams for PCA layout purposes. In the layout design process they create locations on the PCA where capacitors or resistors can be placed.

3.4.1 Scope Channel A - Scope Channel B

See circuit diagrams Figure 9-1 and Figure 9-2.

As the Scope Channel A and B circuits are identical, a description is given for Scope Channel A only.

The Channel A/B circuitry is built-up around a C-ASIC OQ0260. The C-ASIC is placed directly behind the input BNC, and does the analog signal conditioning for the channel.

The C-ASIC OQ0260

Figure 3-3 shows the simplified block diagram of the OQ0260 C-ASIC. The C-ASIC consists of separate input paths for HF and LF signals, an output stage that drives separate HF and LF isolation facilities, and a control block that allows software control of all modes and adjustments. The transition frequency from the LF input path to the HF input path is approximately 10 kHz. The transition frequency of the HF and LF output signal is 25 kHz.

Block Diagram Off Decade Resistance

REFERENCE BUS SUPPLY

Figure 3-3. C-ASIC OQ0260 Block Diagram

REFERENCE BUS SUPPLY

Figure 3-3. C-ASIC OQ0260 Block Diagram

LF input

The LF-input (pin 59) is connected to a LF decade attenuator consisting of an inverting amplifier with switchable external feedback resistors R1031 to R1034. Depending on the selected range the LF attenuation factor which will be set. The input of the LF attenuator is a virtual ground, which is connected to the BNC input via a 1 MQ resistor (R1050...R1052). The LF decade output signal is supplied to a gain adjust stage, and then added to the HF path output signal. The resulting signal is supplied to the C-ASIC output stage.

The AC/DC input coupling relay K1000 is controlled by C-ASIC output ACDC (pin 61), and V1004. The Input B relay is mounted reverse with rtespect to the Input A relay, and has reverse control pulses!

Resistor R1053 limits the discharge current of C1050 when switching from AC coupled to DC coupled input. At AC coupled input, the maximum voltage across C1050 is limited by voltage divider:

(10 MQ of 10:1 probe if connected)+R1050+R1051+R1052 / R1055+R1056. HF input

The HF component of the input signal is connected to a HF decade attenuator via C1001-C1002 (:1) and C1003-C1004 (attenuated). The HF decade attenuator contains four separate current input amplifiers, which are connected to external capacitive dividers: HF0 (:1), HF1 (:10), HF2 (:100), HF3 (:1000). Only one amplifier is active at a time. Inputs of inactive input buffers are internally connected to ground to eliminate crosstalk. To control the DC bias of the buffers inputs, the HF output path voltage is fed back via resistors R1010, R1001, R1002, R1003, and-R1004. To obtain a large HF gain filter R1000/C1000 eliminates HF feed back. The HF attenuator output voltage is supplied to a HF pre-amplifier with switchable gain factors, and then to a gain adjust stage. Finally the HF signal is added to the LF signal. The resulting signal is supplied to the C-ASIC output stage.

Output Stage

The output stage splits the combined HF/LF input signal into a LF and a HF part.

LF output signal

The LF output signal drives a current in the LED of an optocoupler (H1120) via transistor V1120 (output pin 30). For stability the V1120 emitter voltage is fed back to the LF output driver (CLED pin 28). The current in the optocoupler photodiode is converted into a voltage by R1136 and R1133. This voltage (LFA1, LFA2) is measured by a differential amplifier in the S-ASIC (see 3.4.3 Acquisition Section). A copy of the LF output signal is fed back to the C-ASIC to optimize the overall frequency response flatness and to optimize the LF path linearity. The current in the second optocoupler photodiode is converted into a voltage by R1123 and R1124. The voltage (pin 34 and 35) is measured by a differential amplifier in the C-ASIC. The output signal of the amplifier is fed back via filter R1122/C1125.

Fluke Bp190
Figure 3-4. LF Floating to Non-Floating

al-float.wmf

HF output signal

The HF output signal supplies a voltage to the primary side of HF transformer T1100 (C-ASIC pin 40, 41). This voltage is proportional to the input voltage. The voltage at the secondary side of the transformer is referred to the non-floating ground level via R1110, R1111, etc. The secondary voltage (HFA1, HFA2) is supplied to the sampling system S-ASIC (see 3.4.3 Acquisition Section ).

Any HF output DC offset is fed back to C-ASIC pin 32,33 to be eliminated. This prevents saturation and distortion in the HF transformer.

Feedback of the HF signal via C-ASIC pin 37, 38 minimizes the LF-HF turn over error. Due to the parasitic capacitance between the primary and secondary transformer windings, large common mode input voltage steps can cause voltage spikes on the transformer lines. Diodes V1100...1105 will clamp these spikes to the supply voltage. Circuit V1106/C1112/R1112-R1116 limits the consequences of fast common mode voltage spikes caused by for example motor control systems.

Calibration signals (PWMA, CALOUTA)

The PWM output (pin 21) supplies a pulse width modulated square wave to filter/attenuator C1039-R1046-R1068-C1045. By changing the square wave duty cycle, a linear ramp is created for linearization during the pre-cal stage of the calibration. The ramp voltage (LINA) is supplied to pin 62 of the C-ASIC. The PWM output control pulses are supplied by the D-ASIC SDATFLT line to C-ASIC input pin 22 (FASDAT line) via the C-ASIC CONTROL LINEARIZATION circuit (see Figure 9-4). See also below Control - Linearization.

The CALOUT output (pin 49) supplies a -0.5 V or +0.5V voltage to the CALSIG input (pin 53) via R1065, R1049, and R1041 for dynamic (that is periodical during normal operation) gain calibration. The CALOUT voltage is derived from the 1.225V reference diode voltage VREFPA at pin 47.

Control - Linearization

Control information for the C-ASIC, for example selection of the attenuation factor, is sent via the SDATFLT data line to optocoupler H1150. The D-ASIC SCLK line controls the synchronization clock signal SCLKFLT. Optocoupler H1150 transfers the nonfloating control signals to the floating C-ASIC.

SCLK

OFFSETAD

OFFSETAD

SCLKFLT

SDATFLT

R1153

Scope Channel A

Acauisition/Trieeer

R1353

ScQpeChhannelB_

Figure 3-5. C-ASIC Control Circuit

D2000 on the C-ASIC CONTROL LINEARIZATION circuit (see Figure 9-4) connects the SDATFLT line to the D-ASIC SDAT data line, or to the D-ASIC OFFSETAD line. The SDAT line provides the control data to change the C-ASIC settings. The OFFSETAD line provides a Pulse Width Modulated signal that is used for linearization of the C-ASIC during calibration.

Signal LINTAB, supplied by the D-ASIC, controls whether D2000 input pin 12 or 13 is connected to output pin 14.

IREF

A 100 ^A reference current into pin 48 is derived via R1083 from reference diode voltage VREFPA (V1010) for biasing internal C-ASIC circuits.

Supply Voltages

When the test tool is on, the Fly Back Converter on the POWER circuit supplies the primary voltage for supply transformer T1102. The floating secondary voltages are rectified, filtered, and supplied to the C-ASIC.

3.4.2 Meter/Ext Trigger Channel

See Figure 3-6. Meter/Ext Channel Block Diagram, and Circuit Diagram Figure 9-3.

The Meter/Ext Channel can measure voltages up to 1000V, resistance up to 30 MQ, continuity, and diode voltage. It provides no trace but only readings, except in the Trendplot mode. The input is always DC coupled, and the channel has a limited bandwidth of 10 kHz. The Meter/Ext Channel input is floating with respect to Input A and Input B, and with respect to the power supply ground.

The channel can also be used as external trigger input, and as a probe cal generator.

Sony D3202 Ringer Solution

Figure 3-6. Meter/Ext Channel Block Diagram win-ex-block.wmf

Figure 3-6. Meter/Ext Channel Block Diagram

Section 7.5.7 provides a table that shows the control line status for all meter channel functions.

Voltage Measurements

The input voltage Uin is applied to the "volts" attenuation stage via K1500B. This stage consist of opamp N1500 , switch D1500 and resistors R1504-R1507. Possible attenuation factors are :4 (R1504), :40 (R1505), :400 (R1506), and :4000 (R1507). Switch D1501 connects one of the attenuator outputs (pin 1,5,2,4) to the "gain" stage (see below).

Ohms/Continuity/Diode Measurements

A current source (see below) supplies a constant current to the unknown resistance Rx connected to the banana input X1000C pin 5. The current flows via K1500C and PTC resistor R1535. The voltage across the unknown resistor is supplied to the "ohms" buffer N1501A pin 3. The buffered voltage is supplied to D1501 pin 15 (for ranges up to 5 MQ). For the 30 MQ range a :10 voltage is supplied to D1501 pin 14. Switch D1501 supplies the "ohms" voltage to the "gain" stage (see below). In Ohms C1550 is connected to the current source via D1500B pin 11-13 to limit hum influences, specially in the 30 MQ range

Continuity measurements and diode measurements use a current of 0.5 mA. External Triggering

In the External trigger mode the input signal is supplied to the output stage via K1500B, volts attenuator path :4 (R1504, trigger level 120 mV) or :40 (R1505, trigger level 1.2 V), and D1501 pin 1 to 3 or pin 5 to 3.

Reference Source V1550

A +250 mV reference voltage derived from diode V1550 is supplied to D1501 pin 13.

A -250 mV reference voltage is derived from V1550 via R1511-R1509, D1502 pin 14-3, and N1501.

During measuring, occasionally the reference voltage, and the ground (D1501 pin 12) are sensed for calibration.

The -250 mV reference is also added to the Ohms voltage via the gain stage, see "gain stage".

Gain Stage

The gain stage consists of opamp N1501B, switch D1502, and R1508-R1512. It provides:

• a x1 gain for diode measurements, zero calibration, positive reference voltage measurement (internal calibration), and probe calibration (D1502 pin 3 to 1,2,4,5).

• a gain factor x2 in the Volts mode (D1502 pin 3 to pin 13)

• a gain factor 1.2 for the Ohms voltage plus an offset voltage of -0.25 V (D1502 pin 3 to pin 14). By adding the negative offset, a large (line) interference voltage does not cause the hardware to clamp. The software will "filter" the interference voltage.

• a gain factor 6 in the External trigger mode. Output Stage

The voltage at N1501B pin 7 controls the current in the H1525 LED via opamp N1525B and transistor V1525. Via H1525 pin 5-6 the signal is transferred to the S-ASlC LF input (LFEXT1, LFEXT2). The operation is identical to the Input A LF input (see 3.4.1).

Feedback of the LF signal via diode H1525 pin 3-4 and N1525 provides good linearity. The clamp circuits N1515A,B and related parts limit the output voltage to + or - 150 mV. This prevents the S-ASIC and ADC from being overloaded.

Current Source

Reference diode V1555 provides a 1.2 V reference voltage with respect to +5VEXT.

For the 50 nA current (Ohms ranges 5 MQ and 50 MQ), the switches in D1560 are all open. In this case the reference voltage is lowered by a factor 10 by R1556-R1557. The

50 nA current flows via R1558+R1559 and FET V1560 to the input terminal X1000C pin 5. The voltage drop across R1558+R1559 is controlled by feeding it back to the inverting input of N1540B via R1560.

For the higher currents the switches in D1560 are closed in pairs. For the 0.5 mA current D1560 pin 3 is connected to pin 1, and pin 13 is connected to 12. Now R1560 is shorted. The 0.5 mA current flows from +5VEXT, via R1561, D1560, and FET V1560 to the input terminal X1000C pin 5. The voltage drop across R1561 is fed back to N1540B pin 6. The other currents can be set by connecting resistors R1562 (500 |A), R1563 (50 |A), and R1564+R1565+R1565 (5 |A).

Ohms Input Protection and Clamp

When a voltage is applied to the input in the Ohms function V1535, V1536 and V1537 will limit the voltage on the current source. The resulting current is limited by PTC resistor R1535. Under normal conditions the voltage across V1535-V1536 is made zero by buffer amplifier N1540; this prevents measurement errors due to leakage.

The "open input" voltage is limited to about 4 V by FET V1544. The V1544 gate is set to 3 V by N1541 output pin 1. The FET acts as a low leakage diode.

Probe Calibration Output

For DC probe calibration the current source supplies 0.5 mA to R1544 via D1500 pin 13 to pin 12. The resulting 3.1 V is supplied to the red banana input terminal. The voltage is measured by the Meter channel via the Ohms circuit N1501, D1501 pin 14 to 3, etc. The voltage is also measured via the connected probe by Scope channel A or B. From the two measured values a probe correction factor is calculated and applied.

For AC probe adjustment D1572D, R1538 and C1538 generate a 1 kHz square wave voltage on D1572D pin 11. This voltage alternately connects D1500 pin 13 to pin 14 (ground) and pin 12 (R1544). The 0.5 mA current will now result in a 500 Hz 3 V square wave on the red banana input terminal.

Control

Control data and clock signal are supplied to optocoupler H1580 by the D-ASIC (pin P1 and P2) via the SDATEXT data line and the SCLKEXT clock line. The output data and clock are supplied to pulse shapers D1572. Data are shifted into registers D1570 and D1571 on CLK0 (D1572 pin 3). After the last data bit has been shifted into the register, the clock signal CLK is kept low. Now the shift register strobe input signal (D1572 pin 6) goes high and the data appear at the outputs.

Meter Channel linearization

(see C-ASIC CONTROL LINEARIZATION in Figure 9-4)

If the D-ASIC makes line LINTAB (D2000 pin 9,10,11) high, D2000 pin 1 and 15 are interconnected, and D2000 pin 3 and 4 are interconnected. The D-ASIC PWM output signal OFFSETAD is supplied to integrating amplifier N2000. Via D2000 pin 3-4, the resulting analog output voltage is supplied to the S-ASIC Meter/Ext channel input (N2001 pin 59 LFEXT2). This voltage is used for linearization of the Meter channel during calibration.

Supply Voltages

The supply voltages are provided by the Fly Back Converter on the POWER circuit via transformer T1575.

3.4.3 Sampling&Triggering (S-ASIC)

See circuit diagram Figure 9-4.

The core of the Sampling&Triggering section is the S-ASIC, which includes a signal processing section and a trigger processing section section.

Signal path

See Figure 3-7. S-ASIC signal section block diagram and Figure 3-8. S-ASIC Input Circuit.

Schematic Repair Projector Epson 440
Figure 3-7. S-ASIC signal section block diagram

The S-ASIC has the analog input circuits:

1. Input A, for the Scope Channel A HF and LF signals

2. Input B, for the Scope Channel B HF and LF signals

3. Input EXT for the Meter/External Trigger Channel LF signal

The three analog input circuits are identical, except the input EXT circuit that has no HF input. These circuits convert the LF current input signal and the HF voltage input signal into one combined HF+LF signal.

Fpga Real Time Latch
Figure 3-8. S-ASIC Input Circuit

The LF output from the Channel A circuit (see section 3.4.1) controls the current in the LED of H1120. The resulting current in the H1120 photodiode is 5 |A/div., and is converted into a voltage by R1136 and R1133. This voltage (LFA1, LFA2) is measured by a differential amplifier in the S-ASIC. The output signal RLFA1 is supplied to the LF/HF adding point via filter R1132/C1131. For the Meter/Ext input the photodiode (H1525) current is 2.5 |A/div.

The HF output from the input A circuit is supplied to transformer T1100. The secondary transformer voltage is 30 mV/div, and supplied to a differential voltage input of the S-ASIC (HFA1, HFA2) .

The S-ASIC input circuits provide three types of output signals to other internal S-ASIC circuits:

• A current output for the Sample&Memory circuits (not for the Input EXT circuit)

• A voltage output routed directly to the Readout circuit (Direct Path)

• A voltage output for triggering (see Trigger Path below).

The S-ASIC includes a 10 kHz and a 20 MHz bandwidth limiting circuit (C2000 -C2002). For the scope inputs these circuits can be turned on/off via the Input A/B OPTIONS menu.

Sample&Memory

The current output signal supplied to the Sample&Memory circuit represents the measurement signal. The Sample&Memory circuit can operate in two modes, the TCM (Time Conversion Mode) and the WARS (Write And Read Simultaneously) mode.

In time base settings 2 |s/div and faster, the TCM is active. The circuit samples the Input A(B) circuit output current using a high speed current switch. The current samples are converted into voltages by loading various memory capacitors with a current sample. Up to 3000 input signal samples can be stored at a maximum sample rate of 2.5 x 10 samples per second. The sampling clock is generated in the S-ASIC PLL (Phase Locked

Loop). The PLL is synchronized with the external crystal B2000.

The Readout circuit can output the memory capacitor voltages one after another at a lower speed.

In time base setting slower than 2 ^s/div the WARS mode is active. The Input A(B) circuit output signal is sampled at a speed of 20 MS/s (MegaSamples per second). The samples are directly available on the sample and memory output.

Direct path

The Direct Path voltage output supplies the combined HF-LF signal directly to the Readout circuit. The Input A and Input B direct path monitors the input signal. The monitored signal is not given as a measurement result, but is used for control purposes as for example autoranging.

Readout circuits

The input EXT direct path uses the Readout B circuit.

Low temperature coefficient resistors R2050 and R2034 are connected to the S-ASIC Readout stage to obtain a temperature independent current-to-voltage conversion.

The output voltages of the Readout circuits (pin 2 ANAOUTA, pin 119 ANAOUTB) are supplied to an ADC at an output rate of maximal 20 MS/s (CLKJILL to pin 133, see below CLOCK Signals).

The REFADCT reference voltage is supplied to the top of the ADC resistor ladders. To improve the METER accuracy in the WARS mode, a generator in the S-ASIC adds a dither voltage to the measurement signal. Control signals for the generator are RAMPCLK (pin 131) and RSTRAMP (pin 129). The METER/EXT channel uses the same ADC as the Scope Channel B.

Trigger Path

See Figure 3-9. Trigger Circuit for the functional block diagram of the trigger circuit.

fal-trig.wmf

Figure 3-9. Trigger Circuit fal-trig.wmf

Figure 3-9. Trigger Circuit

Depending on the test tool trigger source setting, one of the S-ASIC Input Circuit trigger output signals TRIGEXT, TRIGONB or TRIGONA is supplied to the S-ASIC trigger circuit.

For VIDEO triggering, the trigger signal (composite video) is supplied to the VIDEO CIRCUIT that removes chroma and video information. The output is supplied to the Video Sync separator IC N2020. This IC extracts timing information from the composite sync signal. Used output signals are Odd/Even field, Composite Sync, and Vertical Sync. By changing the current level at the RSET input, the N2020 can be adjusted for video signals with line scan frequencies from 15.625 Hz to 15.750 kHz. For this purpose, the lines SCANRATE1 and SCANRATE2 can be floating or be connected to ground by the CONTROL circuit. The output signals are supplied to the S-ASIC trigger circuit. Only Input A provides Video triggering.

For "NORMAL" triggering, one of the signals TRIGEXT, TRIGONB or TRIGONA is directly supplied to the trigger circuit.

The trigger circuit has two trigger input circuits (TRIGLEVA and TRIGLEVB) that each can compare the input signal to the set trigger levels (TRIGLEV1A-TRIGLEV2A, and TRIGLEV1B-TRIGLEV2B). The analog trigger level voltages are supplied by the D-ASIC by means of filtered PWM (Pulse Width Modulated) signals. Each trigger input circuit generates a trigger signal if the input signal crosses the trigger levels. To prevent triggering on noisy signals a large trigger gap can be created by setting the two trigger levels of each trigger input circuit.

The trigger circuit provides three output signals:

• ALLTRIG includes all triggers (all trigger level crossings).

• TRIGDT gives the final acquisition trigger for the D-ASIC in WARS mode, and is not used in TCM mode.

TRIGDT can be a qualified trigger, for example at Scope Pulse Triggering with trigger condition >T (e.g. > 10 ms), TRIGDT gives a trigger pulse if the input pulse meets the condition > 10 ms; TRIGDT can also be equal to the ALLTRIG signal.

• EXTTRIG is used to supply an odd/even field indication for video triggering to the D-ASIC. In normal trigger mode EXTTRIG can be used for triggering on a time slot.

Control signals for the trigger circuit are:

• HOLDOFF releases the trigger system. It goes low if the acquisition system is able to validate new triggers. HOLDOFF is supplied by the D-ASIC (pin B17).

• TRIGQUAL (or TRIGQUALJ in the old Main PCA) qualifies (conditions) the trigger to be supplied to the TRIGDT output. For example at video triggering on line n, the ALLTRIG triggers are counted down and only trigger n is passed to the TRIGDT output.

In the OLD Main PCA version, the TRIGQUALJ signal is supplied by the trigger qualifier extender circuit D3202-D3203, see circuit diagram Figure 9-5. The circuit qualifies triggers in the Trigger on Pulse Width mode for short pulses (< 300 ns). Without this circuit the system is unable to qualify short pulses due to (software) processing time.

If the ENSHPULS line is low, the TRIGQUAL signal is directly routed to the TRIGQUALJ output. If the ENSHPULS line is high, the circuit generates a new trigger qualifier signal TRIGQUALJ.

In the NEW Main PCA version the TRIGQUAL signal is directly supplied by the D-ASIC.

RAMP

The RSTRAMP and RAMPCLK control a dither signal generator. The output signal of this generator is used to improve the measuring accuracy.

Control (data/address buffer)

Via the buffered address/data bus (D2001, D2002) the D-ASIC can program the S-ASIC as required by the firmware.

The Read and Write control signals are derived from the ROMRD# and ROMWR# signals supplied by the D-ASIC.

CLOCK Signals

Crystal B2000 provides the synchronization clock signal for the TCM mode PLL oscillator (high sample rate).

The 20 MHz CLKJILL clock signal (pin 133) is used for readout of the samples, and is supplied by the D-ASIC (pin B18). During a high sample rate acquisition in the S-ASIC TCM mode, the INTRP line (S-ASIC pin 8 to D-ASIC pin A18) tells the D-ASIC to turn this clock off. This prevents the input signal samples from being influenced by the CLKJILL signal.

C-ASIC Control Linearization.

The C-ASIC Control Linearization circuit is used for control of the input circuits (see section 3.4.1) and the linearization of the Meter channel (see section 3.4.2).

3.4.4 S-ASIC supply

See circuit diagram Figure 9-5.

The S-ASIC supply section provides mutually decoupled supply voltages for the various circuits in the S-ASIC.

The supply voltages V1P5TOA (S-ASIC pin 17) and V1P5TOB (S-ASIC pin 95) control the offset voltage of the S-ASIC output signal in TCM mode (time base 2 ^s or faster, see preceding section "Sample&Memory" ). They are derived from the REFADCT voltage, and from PWM controlled voltages supplied by the D-ASIC (pins C13 and D12). The voltages are set to such a value that the offset difference between TCM mode and WARS mode is zero. If the offset difference is not eliminated, AUTORANGE and OL (OverLoad) indication will not function correctly.

For the QUALIFIER EXTENDER circuit (D3202, D3203) see section 3.4.3, sub section "Trigger Path".

See circuit diagram Figure 9-6.

The S-ASIC output voltages are supplied to ADC Channel A and ADC Channel B. The Meter/External Trigger channel uses the ADC Channel B. The ADC's sample the analog voltages, and convert them into 8-bit data bytes (D0-D7). The sample rate is 20 MHz. The sample clock SMPCLK is providd to pin 15 (new) or 24 (old). The output data are read and processed by the D-ASIC on the Digital Control section..

The reference voltage REFADCT (from S-ASIC pin 157) determines the input voltage swing that corresponds to an output data swing of 00000000 to 11111111 (D0-D7).

3.4.6 Digital Control

See circuit diagram Figure 9-7.

The Digital circuit is built up around the D-ASIC D3500. It provides the following functions:

• ADC data acquisition and processing for traces and numerical readings

• Trigger processing

• Microprocessor, Flash EPROM and RAM control

• Display control

• Keyboard control, ON/OFF control

• Miscellaneous functions, as PWM signal generation, SDA-SCL serial data control, probe detection, Slow ADC control, serial RS232 interface control, buzzer control, etc.

D-ASIC, RAM, ROM Supply

The D-ASIC is permanently powered by the +3V3GAR voltage supplied by the Power Circuit if at least the battery pack is present (+VD after filtering). The P-ASIC indicates the status of the +3V3GAR voltage via the VDDVAL line connected to D-ASIC pin N2. If +3V3GAR is >3V, VDDVAL is high, and the D-ASIC will start-up. As a result D-ASIC functions are operative regardless of the test tool ON/OFF status.

The RAM supply voltage +VDR2 and FlashROM supply voltage +VF are also derived from +3V3GAR.

Controlled switch off

The programmable logic device D3550 provides a controlled power down of the D-ASIC. In case of a non-controlled power down, a 6 mA D-ASIC supply current can flow after switching the test tool off. The normal D-ASIC supply current at power of is about 140 ^A.

Watchdog

In case a software hang-up arises, the watchdog circuit D3507 will reset the D-ASIC to re-start the software.

ADC data acquisition

The test tool software starts an acquisition cycle. The D-ASIC acquires the sample data from the ADC, and stores them internally in a Fast Acquisition Memory (FAM). A separate MIN/MAX FAM stores the samples with the highest and lowest value. From the FAMs the required ADC data are processed and output as LCD control data. Data can also be output via the UART to the optical RS232 interface.

Triggering

The D-ASIC controls an processes the trigger control signals HOLDOFF, TRIGDT, ALLTRIG, EXTTRIG and TRIGQUAL. See 3.4.4 sub section Trigger Path for a description of these signals.

Microprocessor, ROM and RAM control, mask ROM For control purposes the D-ASIC includes a microprocessor.

The instrument software is loaded in Flash ROM located on the Flash/SRAM module A1 that is inserted into X3501.

The Flash/SRAM module also has RAM for temporary data storage.

The Flash/SRAM module for the OLD and the NEW Main PCA units are NOT equal.

Additional RAM is provided by D3502 and D3503 (D3503 for OLD Main PCA only). This RAM is used for, amongst others, the video information.

The D-ASIC has on-chip mask boot ROM. If no valid Flash ROM software is present when the test tool is turned on, the mask ROM software will become active. The test tool can be forced to stay in the mask ROM software by pressing and holding the A and > key, and then turning the test tool on. When active, the mask ROM software generates a HF triangular wave on measurement spot MS3603 (pinC5 of the D-ASIC, Row 1).

Display Control

The displayed screen consists of:

• information that is captured by the acquisition system, and is then processed and displayed (e.g. traces and numerical readings). This information is stored in RAM.

• information that is permanently stored in the test tool FlashROM memory, so called bitplanes (e.g. grids).

The D-ASIC supplies the LCD data and control signals to the LCD control circuit (section 3.4.7).

Keyboard Control, ON/OFF Control

The keys are arranged in a 6 rows x 6 columns matrix. The D-ASIC drives the rows, and senses the columns, see Figure 3-10. Initially the ROW lines are low, the column lines are high via a pull-up resistance in the D-ASIC. If a key is pressed a column line goes low, and causes an interrupt. Then the D-ASIC supplies pulses to the sequential ROW lines, and senses the column lines to detect which key is pressed.

0V ROW

Press key

s 50 ms

500 ^s pulses

Release key

COLUMN

Press key

50 ms I

500 pulses

Release key

Figure 3-10. Keyboard Control Signals

The ON/OFF key is not included in the matrix. This key toggles a flip-flop in the D-ASIC via the ONKEY line (D-ASIC pin F4). As the D-ASIC is permanently powered by +3V3VGAR, the flip-flop can signal the test tool on/off status.

PWM Signals

The D-ASIC generates various pulse signals, by alternately connecting an output port to a reference voltage (REFPWM1 or REFPWM2) and ground(PWMA, PWMB pins 2640). The duty cycle of the pulses is controlled by the software. By filtering the pulses in low pass filters (RC), software controlled DC voltages are generated. The voltages are used for various control purposes, see Table 3-3.

Table 3-3. D-ASIC PWM Signals

PWM signal

Function

Destination

Reference

TRGLV1AD, TRIGLV2AD TRGLV1BD, TRIGLV2BD

Trigger level control

S-ASIC

REFPWM1

OFFSETAD

Meter/Ext linearization

D2000

REFPWM1

BACKBRIG

Back light brightness control

Back light converter

REFPWM1

CONTR-D

Display contrast control

LCD unit

REFPWM1

DDTOFSA, DDTOFSB

S-ASIC offset control

S-ASIC

REFPWM1

SADCLEVD

Slow ADC comparator voltage

SLOW ADC

REFPWM2

CHARCURD

Battery charge current control

P-ASIC

REFPWM2

Serial Bus SDAT/SCLK - SDATEXT/SCLKEXT

The D-ASIC SDAT line (pin A2) is used to send control data to the C-ASIC's via the D2000 on the C-ASIC CONTROL LINEARIZATION circuit (Fig.9-4). The LINTAB signal (pin R5) controls D2000. The SCLK line (pin A3) transmits the 1.25 MHz synchronization clock .

The SDATEXT line pin P2 used to send control data to the Meter/External Trigger channel. The SCLKEXT line pin P1 transmits the synchronization clock.

D-ASIC Clocks

A 32 kHz oscillator runs if the 3V3GAR supply voltage is present, so if any power source is present (crystal B3501). The clock activates Power On/Off control circuit, and the real time clock (time and date).

A 40 MHz oscillator runs if the test tool is ON, and/or if the power adapter voltage is present (crystal B3502).

A 3.6864 MHz UART oscillator for the Serial RS232 communication runs if the 40 MHz oscillator runs (crystal B3500).

Buzzer

The buzzer is directly driven by a 4 kHz square wave from the D-ASIC (pin T4) via FET V4211. If the test tool is on, the +30VD supply from the Fly Back converter is present, and the buzzer sounds loudly. If the +30VD is not present, e.g. when the Mask (boot) software runs, the buzzer sounds weak.

3.4.7 LCD Control

See circuit diagram Figure 9-8.

The Liquid Crystal Display is built up of 320 columns of 240 pixels each. It is located on the LCD unit, which also includes the LCD drivers and the fluorescent back light lamp. The unit is connected to the main board via connector X3601.

The D-ASIC (Fig. 9-7) provides the LCD control signals to D3601 and D3602:

• LCDDATA0...7 + DATACLK: display data for the display column drivers

On the NEW Main PCA D3700 is installed to change the LCDDATA0-4 signal order. This order is different for a color LCD and b/w LCD.

• FRAME: during a frame pulse the LCD picture is refreshed

• LINECLCK: sequentially transfers the data to the column driver outputs.

• DISPON: turns the display on or off

• M_ENAB: back plane modulation signal, see below.

The LCD supply circuit generates various voltage levels V0...V4 for the LCD. The various levels are supplied to the driver outputs, depending on the supplied data and the M(ultiplex) signal. The M signal (back plane modulation) is used by the LCD drivers to supply the various DC voltages in such an order, that the average voltage does not contain a DC component. A DC component in the LCD drive voltage may cause memory effects in the LCD.

The CONTRAST voltage controls the LCD contrast by changing the LCD Supply voltages. Is controlled by a D-ASIC PWM signal (pin A10, CONTR-D) to PWM filter R3311/C3310. The voltage REFPWM1 is used as bias voltage for the contrast adjustment amplifier N3600.

3.4.8 Power

See circuit diagram Figure 9-9.

Power Sources , Operating Modes

Figure 3-11 shows a simplified diagram of the power supply and battery charger circuit.

FLY BACK CONVERTER

FROM POWER ADAPTER

CHARGER/CONVERTER V4102 L410x

R4112_

VBATHIG

TEMPHI

CHASENS

CHASENS

R4114 IIMAXCH

VCHDRIV

R4120 VADALOW

Amplify Level

CHARGE CONTROL

supply for charge control circuit

POWER ASIC

COSC

"^C4123

V4111 V4112

MAINVAI

P7VCH

Figure 3-11. Power Supply Block Diagram

As described in Section 3.3 the test tool operating mode depends on the connected power source.

R4110

C4112

The voltage VBAT is supplied either by the power adapter via V4102/L410x, or by the battery pack. It powers a part of the P-ASIC via R4112 to pin 60 (VBATSUP). If the test tool is off, the Fly Back Converter is off, and VBAT powers the D-ASIC via transistor V4000 (+3V3GAR). This +3V3GAR voltage is controlled and sensed by the P-ASIC. If it is NOT OK (<3.05V), the output VDDVAL (pin 64) is low. The VDDVAL line is connected to the D-ASIC, and if the line is low, the D-ASIC is inactive: the test tool is in the Idle mode. A low VDDVAL line operates as a reset for the D-ASIC.

If VDDVAL is high (+3V3GAR > 3.05 V), the D-ASIC becomes active, and the Off mode is entered. The D-ASIC monitors the P-ASIC output pin 12 via V4111-V4112 (MAINVAL), which indicates the presence of the power adapter voltage (high = present). The D-ASIC also monitors the test tool ON/OFF status (by pressing the ON/OFF key, a bit in the D-ASIC, indicating the test tool ON/OFF status is toggled). If neither a correct power adapter voltage is supplied (MAINVAL is low), nor the test tool is turned on, the Off mode will be maintained.

If a correct power adapter voltage is supplied (MAINVAL high), or if the test tool is turned on, the mask software starts up. The mask software checks if valid instrument software is present. If not, e.g. no instrument firmware is loaded, the mask software will keep running, and the test tool is not operative: the test tool is in the Mask active state. For test purposes the mask active mode can also be entered by pressing the A and > key when the test tool is turned on.

If valid software is present, one of the three modes Operational, Operational & Charge or Charge will become active. The Charger/Converter circuit is active in the Operational & Charge and in the Charge mode. The Fly back converter is active in the Operational and in the Operational & Charge mode.

Charger/Converter (See Figure 3-11.)

The power adapter powers the Charge Control circuit in the P-ASIC via an internal linear regulator. The power adapter voltage is applied to R4104. The Charger/Converter circuit controls the battery charge current. If a charged battery pack is installed, the nominal VBAT is 7.2 V (up to 9 V). If no battery pack is installed, VBAT is about 11 V. The voltage VBAT is supplied to the battery pack, to the P-ASIC, to the Fly Back Converter, and to transistor V4000. The FET control signal CHAGATE is a 100 kHz square wave voltage with a variable duty cycle , supplied by the P-ASIC Control circuit. The duty cycle determines the amount of energy loaded into L410x/C4114. By controlling the voltage VBAT, the battery charge current can be controlled. The various test tool circuits are supplied by the Fly Back Converter, and/or V4000.

Required power adapter voltage

The P-ASIC supplies a current to reference resistor R4120 (VADALOW pin 8). It compares the voltage on R4120 to the power adapter voltage VADAPTER on pin 20 (supplied via R4110, and attenuated in the P-ASIC). If the power adapter voltage is below 14 V, the P-ASIC output pin 12, and the line MAINVAL, are low. This signal on pin 12 is also supplied to the P-ASIC internal control circuit, which then makes the CHAGATE signal high. As a result FET V4102 becomes non-conductive, and the Charger/Converter is off.

Battery charge current

The actual charge current is sensed via resistor R4101, and filter R4103-C4102, on pin 9 of the P-ASIC (IBATP). The sense voltage is supplied to the control circuit in the P-ASIC. The required charge current information is supplied by the D-ASIC via the

CHARCUR line and filter R4121-C4122 to pin 80. A control loop in the control circuit adjusts the actual charge current to the required value.

Depending on the required charge current the filtered CHARCUR voltage range on pin 80 is:

• 2.7 V for no charge current (0 A), for example if the battery temperature limit is exceeded (>50 °C)

• > 3 Volt if the charger converter is off (V4102 permanently non-conductive). This happens for example if no BC190 is connected

The D-ASIC derives the required charge current value from the battery voltage VBAT. The D-ASIC measures this voltage via the Slow ADC (see 3.4.9. Slow ADC). The momentary value, and the temperate change as a function of time (-dT/dt), are used as control parameters. If the dT/dt exceeds 0.75 °C per minute the battery is full.

Battery low indication

The battery empty indication on the LCD is given for a battery voltage < 6.9 V. If the voltage drops below 6.0 V, the test tool turns off.

Charging the battery

Battery Refresh

If a battery refresh is started the following actions are performed:

• the 1 A charge current is applied to the battery until it is full

• the charger is turned off, and as much as possible circuits are activated in order to discharge the battery in the shortest time. The initial discharge current is about 1 A.

• when the battery is discharged (battery voltage < 6.4 V) the 1 A charge current is applied until the battery is full; then the 90 mA charge current is applied continuosly.

Battery Charger BC190 connected, test tool off, battery completely discharged

• the 1 A charge current is applied until the battery is full (takes about 3.5 hrs)

• the 0.35 A charge current is applied for 2 hrs.

• the 90 mA charge current is applied continuosly. Battery Charger BC190 connected, test tool on

• the 60 mA charge current is applied continuosly.

Battery temperature monitoring

The P-ASIC supplies a current to a NTC resistor in the battery pack (TEMP pin 5, battery connector pin 3). The P-ASIC conditions the voltage on pin 5 and supplies it to output pin 79 BATTEMP. The D-ASIC measures this voltage via the slow ADC. It uses the BATTEMP voltage for control purposes (set charge current).

Additionally the temperature is monitored by the P-ASIC. The P-ASIC supplies a current to reference resistor R4102 (TEMPHI pin 4), and compares the resulting TEMPHI voltage to the voltage on pin 5 (TEMP). If the battery temperature is too high, the P-ASIC Control circuit will set the charge current to zero, in case the D-ASIC fails to do this.

During charging, the measured temperate change as a function of time (-dT/dt) is used to see if the battery is completely charged.

If the battery temperature monitoring system fails, a temperature switch in the battery pack interrupts the battery current if the temperature becomes higher then 70 °C

Maximum VBAT

The P-ASIC supplies a current to reference resistor R4113 (VBATHIGH pin 7). It compares the voltage on R4113 to the battery voltage VBAT on pin 3 (after being attenuated in the P-ASIC). The P-ASIC limits the voltage VBAT to 11 V via its internal Control circuit. This situation arises in case no battery or a defective battery (open) is present.

Battery Identity

The BATTIDENT line (pin 90) is connected to R4100 on the Power Circuit, and to a resistor in the battery pack. The voltage level indicates the installed battery type. If the battery is removed, the BATTIDENT line goes high.

Charger/Converter input current

The input current is sensed by R4104. The P-ASIC supplies a reference current to R4114. The P-ASIC compares the voltage drop on R4104 (CHASENSP-CHASENSN pin 14 and 15) to the voltage on R4114 (IMAXCHA pin 6). It limits the input current (e.g. when loading C4114 and C4000/C4001 just after connecting the power adapter) via its internal Control circuit.

CHAGATE control signal

The CHARGE CONTROL circuit in the P-ASIC supplies the CHAGATE control signal. The control circuit end stage supply voltage is VCHDRIVE. The CHAGATE high level makes V4102 non-conductive ("OFF", Vgs > 0). The CHAGATE low level is limited to VCHDRIVE minus 13V, and makes V4102 conductive ("ON", Vgs negative).

TH7TTI V4102 "OFF"

Figure 3-12. CHAGATE Control Voltage

+3V3GAR Voltage

When the test tool is not turned on, the Fly Back Converter does not run. In this situation, the +3V3GAR voltage for the D-ASIC, the FlashROM, and the RAM is supplied via transistor V4000. The voltage is controlled by the VGARDRV signal supplied by the P-ASIC (pin 69). The current sense voltage across R4000 is supplied to pin 70 (VGARCURR). The voltage +3V3GAR is sensed on pin 66 for regulation. The internal regulator in the P-ASIC regulates the +3V3GAR voltage, and limits the current.

VCHDRIVE VCHDRIVE -13V

Reference voltage REFPWM2

The +3.3 V voltage REFPWM2 is used as reference voltage for one of the PWM circuits in the D-ASIC. It is derived from reference diode V4114, as shown in Figure 3-13. REFPWM2 circuit.

Analog Switch
Figure 3-13. REFPWM2 circuit

Fly Back Converter

When the test tool is turned on, the D-ASIC makes the PWRON line (P-ASIC pin 62) high. Then the self oscillating Fly Back Converter becomes active. It is started up by the internal 100 kHz oscillator that is also used for the Charger/Converter circuit. First the FLYGATE signal (pin 49) turns FET V4001 on (see Figure 3-14), and an increasing current flows in the primary transformer winding to ground, via sense resistor R4003. If the voltage FLYSENSP across this resistor exceeds a certain value, the P-ASIC turns FET V4001 off. Then a decreasing current flows in the secondary windings to ground. If the windings are "empty" (all energy transferred), the voltage VCOIL sensed by the P-ASIC (pin 52) via R4001 is zero, and the FLYGATE signal will turn FET V4001 on again.

V4001 "OFF"

Figure 3-14. Fly-Back Converter Current and Control Voltage

V4001 "OFF"

Figure 3-14. Fly-Back Converter Current and Control Voltage

The output voltage is regulated by feeding back a part of the +3V45 output voltage via attenuator R4011-R4012-R4013 to pin 54 (VSENS). This voltage is compared in the P-ASIC to a 1.23 V reference voltage. Any deviation of the +3V45 voltage from the required 3.45 V changes the current level at which current FET V4001 will be switched off. If the output voltage increases, the current level at which V4001 is switched off will become lower, and less energy is transferred to the secondary winding. As a result the output voltage will become lower.

An current source in the P-ASIC supplies a current to R4020. The resulting voltage is a reference for the maximum allowable primary current (IMAXFLY). The voltage across the sense resistor (FLYSENSP) is compared in the P-ASIC to the IMAXFLY voltage. If the current exceeds the set limit, FET V4001 will be turned off.

Another internal current source supplies a current to R4014. This resulting voltage is a reference for the maximum allowable output voltage (VOUTHI). The secondary output voltage -1V8 is supplied to the P-ASIC, and then compared to the VOUTHI voltage. If the voltage -1V8 exceeds the set limit, FET V4001 will be turned off.

The FREQPS signal drives the P-ASIC output stage that supplies the FET drive FLYGATE signal. It is also supplied to the D-ASIC, in order to detect if the Fly Back converter is running within specified frequency limits (used in factory test only).

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