The A6 Digital Synthesis PCA contains the following functional blocks:
• Precision, dual tracking, +/-7 V references
• Two precision, 28 bit, pulse width modulated, digital to analog converters (DAC's)
• A 500 kHz, dual channel, variable phase, arbitrary waveform generator
• A 0.33 V - 1000 V sense divider and buffer amplifier
• Two ac/dc averaging converters
• Two amplitude control loops, for dual channel operation
• An 18 bit analog to digital (A/D) converter with input mux and variable gain amplifier
• A thermocouple based temperature sourcing and measuring circuit
• Digital control circuitry consisting of octal latches, relay drivers, and a high speed serial link to the main CPU.
These functional blocks, when used with the A8 High Voltage PCA, and/or A7 Current PCA, provide single or dual channel ac/dc V/A/W, offset table and nonsinusoidal waveforms, duty cycle, temperature measuring and sourcing, internal calibration and diagnostics, and digital control over all the analog assemblies. A brief description of each block is described below.
Precision, Dual Tracking, +/-7 V References
Refer to Sheet 2 of the A6 Digital Synthesis PCA schematic.
The reference circuit is based on the ref amp set used in the 8842A. Reference amplifier, Q1, and op amp, U38, along with Z3 and Z4 generate a trimmed -7 V reference. This reference is inverted by a flying capacitor inverter circuit consisting of U76, C60 and C74, and buffered by U27. Each reference is also buffered by a discrete output stage; Q4 & Q5.
Precision, 28bit, PWM, Dual DAC's
Refer to Sheet 2 of the A6 Digital Synthesis PCA schematic.
Since the two precision DAC's are identical, only the voltage channel DAC will be described. This DAC design uses pulse width modulation (PWM) to convert a digital value to a precise analog voltage. The duty cycle is generated by programmable counter logic contained in an FPGA, U5. The counters are 14 bit binary, operating off of the 10Mhz clock, generating a variable duty factor pulse train at a frequency of 610.3515Hz. The duty cycle has a resolution of 1 part in 16384 (14bits).
This variable duty cycle is complemented and deskewed by a D flip flop and outputted from the FPGA as DAC1PREF and DAC1NREF, driving the gate pins of a quad analog switch, U45. U45 alternately connects the input of the DAC filter, Z10, to the +/-7 V references. The output of this filter which consists of Z10, R75,R76, U28, and C76-78, will have a voltage equal to the average value of the voltage at its input.
D = N/16384 where N is the value that the timer is programmed to.
U52 and Z10 are used to cancel the resistance of U45, while U58 and Z2 buffer the output and divide it by two.
To obtain an additional 14bits of resolution, another PWM channel is generated and output at U18-12. This signal is inverted by U19A, divided by R70, R72, and R73, and summed into the filter at C76.
DC Voltage Operation
Refer to Sheet 3 of the A6 Digital Synthesis PCA schematic.
In the 3.3 V dc range the VDAC output from Z2 is applied to the non-inverting input of the control loop integrator, U60. The output of U60 is inverted by U87B and is buffered by the 3.3 V output amp, U42, and switched to VMID by K8. VMID is switched to the instrument output by the A3 Motherboard PCA relay A3-K3. This output is sensed by NSNS_HI and switched to VDIV by A3-K2. VDIV is applied to the sense divider, Z5, by K3. The composite sense amplifier, U57 and U21, invert the sense signal which is then applied to the inverting input of U60. The net result is an instrument output dc voltage that is equal to -VDAC.
The 33 V dc range operates in a similar way, except the inverting amp, U87B, is bypassed by switch U48D and the output of U42 is amplified and inverted by the A8 High. The output of the A8 High Voltage PCA is applied to VMID and the 33 V sense input is selected by K2.
The 330 m V dc range does not use the sense divider/amplifier, but instead receives its feedback through analog switch U15A. U87B is bypassed in this range so there is no inversion in this mode of operation. The output of U42 is then divided by 10 by Z8, with the output of Z8 connected to VMID by K7.
The 330 V dc and 1000 V dc ranges are generated by rectifying a high voltage ac signal. First the output of U25, a DDS generated 2kHz square wave, is switched to the input of U42 by switch U48C. This square wave is amplified, stepped up, rectified and filtered by the A8 High Voltage PCA to approximately the desired dc voltage. This dc voltage is then connected to VDIV for connection to the instrument output and for sensing. In the case of the 330 V range, VDIV is connected to the sense divider/amplifier by K1. In the 1000 V range, U98 is used to invert the signal on VDIV. This divided voltage is applied to U60, which generates an error signal. This error signal is fed back to U49 (Sheet 1 of the A6 Digital Synthesis PCA schematic) for inversion and amplification before being applied to the multiplying reference pin of the DDS waveform generation DAC, U13. The voltage at this pin controls the amplitude of the ac square wave, thus adjusting the dc voltage to exactly the desired value.
DDS Waveform Generation
Refer to Sheets 1 and 8 of the A6 Digital Synthesis PCA schematic.
Direct digital synthesis was first used at Fluke in the modulation oscillator of the 6080A synthesized signal generator. It uses a high speed waveform reconstruction DAC, digital phase accumulator, and a waveform lookup table to generate repetitive ac signals of arbitrary waveform. A modified and improved circuit, based on the same technique is contained in the FPGA, U5. The DDS circuit uses a 40 phase accumulator and uses SRAM, U1 to store the wave tables. Each memory location in the SRAM wave table corresponds to a phase. The value of each location in the wave table is the instantaneous amplitude value of the waveform for that particular phase. As the phase accumulator sequences through address locations the amplitude data is routed to the 16 bit DDS DAC's (U13, U44) where, point by point, the waveform is generated.
The FPGA splits the addresses into two channels where the address of the secondary channel can be offset from the first, thereby causing a phase difference between the two. It also provides logic for writing the waveform data to the table.
The differential output current of the primary DDS DAC (U13) is converted to a voltage of about 9.7 V p-p by R41,R47 and U4. It is then filtered to remove glitches and clock feed thru and adjusted in amplitude by the scaling DAC, U53 & U25. This voltage can be further adjusted by adjusting the current flowing into U13's IREFIN pin. This is done by amplifying the control loop error voltage by an amount inversely proportional the scaling DAC's attenuation and applying it through R11 to the U13 pin 24.
The secondary DDS channel works in a similar way.
AC Voltage Operation
Refer to Sheet 3 of the A6 Digital Synthesis PCA schematic.
The output of the primary DDS channel is routed to the 3.3 V output amplifier, U42, through switch U48. This amplified/divided, outputted and sensed the same as for V dc except instead of the sense amplifier output being applied to the loop integrator, it is first converted to a dc voltage by an average responding ac/dc converter, U40, U20, Q2, Q3, CR5, U39. This dc voltage is filtered and buffered by U84 and U3, and switched into the loop integrator by U15. As in dc the loop integrator reference pin has the VDAC signal on it. The difference between the VDAC and the output of the averaging converter is integrated and applied to the DDS DAC IREFIN pin. This adjusts the output voltage of the DDS DAC, U13, until the difference is zero.
DC Current Operation
Refer to Sheets 2 and 4 of the A6 Digital Synthesis PCA schematic.
In all the dc current ranges the IDAC output from Z1 is applied to the noninverting input of the control loop integrator, U9. The output of U9 is switched to I_AC/DC by U33A. This signal is converted to a high impedance current source by the transconductance amplifier on the A7 Current PCA. This current is routed to the AUX HI output and flows through the UUT, returning into AUX LO terminal. It then passes through a shunt on the A7 Current PCA, converting it back into a voltage, I_FBK. I_FBK is switched to the inverting input of U9 by U31, which integrates the difference between its two inputs, forcing them to be equal.
In all the ac current ranges, the second DDS channel from U34 is switched to I_ACDC by U33C. This signal is converted to a current, outputted, and fed back on I_FBK the same way as for dc currents. In AC, I_FBK is switched to the input of U14B where it is rectified and filtered by U14A, CR1, U84A and U3 before it is switched into the negative input of the error integrator, U9. U9 integrates the difference between this feedback signal and the IDAC output, generating an error signal. This error signal is amplified by the loop compensation DAC, U47, and U90 and then routed to the reference pin of the DDS waveform DAC, U44, adjusting the output until the difference between the inputs of U9 is zero.
Thermocouples consist of a pair of wires that are each made of different metals or alloys. On one end of this pair, the wires are electrically connected to each other. The other end is terminated to copper contacts fastened to an isothermal block. The voltage produced at the iso-thermal block is a function of the thermocouple type and the temperature difference between the iso-thermal block and the end of the wire pair. Thus, to measure the temperature of a thermocouple, its voltage, and the temperature of the iso-thermal block must be measured.
Iso-thermal Block Reference Junction Temperature Measurement
Refer to Sheet 5 of the A6 Digital Synthesis PCA schematic.
The iso-thermal block contains two copper buttons to connect to the thermocouple plug, a precision 10 kQ bead themistor glued between the buttons, and a 6-layer PWB. It is constructed to maintain as low a temperature difference between the buttons and the transistor as possible. The thermistor is biased with a programmable current sink via TC_ISO_SRC. This current sink consists of U97, U6, R108, R126, and R127 and provides about 10 ^A, developing about 1 V across the thermistor. The voltage of the themistor is measured by connecting TC_ISO to the A/D input with U82A.
Thermocouple Voltage Measurement:
The thermocouple voltage is multiplied by 10 on the A10 Isothermal PCA. It is then switched into the A/D by U82. The A7A10 Isothermal PCA is assembled and tested as part of the A7 Current PCA.
All that is required to simulate a thermocouple is source a voltage that would be generated by a thermocouple at that temperature. The reference junction is measured to determine the temperature of the isothermal block. Then this temperature and the requested temperature are used to determine the correct output voltage. This voltage is generated by the 3.3 DC range, buffered by U13 and divided by 10 on the A10 Isothermal PCA before being outputted on the thermocouple connector.
Analog to Digital Converter
Refer to Sheet 4 on the A6 Digital Synthesis PCA schematic.
All internal calibration and diagnostic measurements are buffered by a gain programmable instrumentation amplifier, U10. The gain of this amplifier is selected by closing U82D (X10), closing U82C (/40) or by leaving both open (X1). The output of U10 is applied to the A/D, U30 where it is converted into a digital value to be read by the micro-controller.
Refer to Sheet 7 of the A6 Digital Synthesis PCA schematic.
In order to minimize damage caused by misuse, abuse, component malfunction, or software errors, a fault detection circuit was incorporated into the Calibrator. It consists of a set/reset fault latch, a power MOSFET for driving reset coils, and various fault detecting comparators. On the A6 Digital Synthesis PCA, the only kind of faults detected are destructive voltages present at the instrument output during voltage mode operation. This type of fault is detected with a window comparator, U50, that monitors the output of the sense buffer, U21. When the output of U21 exceeds +/-10 V the output of U50 goes low, setting the fault latch, U16. The output of the fault latch sets the signal CLR_DRVR hi, disabling all the latching relay drivers, and turns on Q6, which resets all the latching relays connected to REL_RST*. The fault latch also signals the FPGA of a fault condition via the IG_FAULT signal, allowing the software to respond appropriately. In the case of the DDS assembly, a fault condition disconnects all DDS relays that are connected to the output.
The FAULT*, REL_RST*, and CLR_DRVR signals are also routed to the A3 Motherboard PCA, allowing any other assembly to detect and respond to any abnormal conditions as needed.
Refer to Sheet 8 of A6 Digital Synthesis PCA schematic.
The inguard analog circuitry is controlled through an FPGA, U5. U5 contains a 1 megabit/s serial link, a serial to parallel shift register, and a state machine to provide a microprocessor style data, address and control signals. U5 also incorporates six PWM circuits for DAC's and a two channel DDS circuit with phase adjust and phase error measurement. There are also some general purpose registers for control of the analog circuitry.
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