234 Digital Kernel

The Digital Kernel is composed of six functional circuit blocks: the RS-232 interface, the Microprocessor, the EEROM (Electrically Erasable Read Only Memory), the RAM (Random Access Memory), the ROM (Read Only Memory), and the IEEE-488 Option Connections. These blocks are described in the following paragraphs.

2-35. RS-232 Interface

The RS-232 interface is composed of connector A1J5, RS-232 level shifter A1U7 and the hardware serial communication interface (SCI) in Microprocessor A1U6.

The transmit signal from the SCI (A1U6-14) goes to the RS-232 driver (A1U7-12), where it is inverted and shifted to transition between approximately +5.0 and -5.0 V dc. When nothing is being transmitted by the meter, the driver output A1U7-5 is -5.0 V dc. The receive signal from A1J5 goes to the RS-232 receiver A1U7-4, where it is inverted and shifted to transition between +5.0 and 0 V dc. When nothing is being transmitted to the meter, the receiver output A1U7-13 is +5.0 V dc.

Data Terminal Ready (DTR) is a modem control signal controlled by the Microprocessor. This signal is an RS-232 output generated by driver A1U7-7; it is at +5.0 V dc when the meter is powered up.

2-36. Microprocessor

The Microprocessor utilizes an eight-bit data bus and a sixteen-bit address bus to access memory locations in ROM (A1U8), RAM (A1U10), and the IEEE-488 option. The upper three bits of the address bus are decoded by A1U9 to generate chip select signals for the ROM (A1U9-6) and RAM (A1U9-8). The Microprocessor enables the reading of memory by driving RD* (A1U6-67) low, and writing of memory by driving WR* (A1U6-66) low. The IEEE-488 option also makes use of the signal R/W* (read when high, write when low) that is generated by A1U6-65.

The Microprocessor operates with a memory cycle time of 1.085 us as determined by the 3.6864 MHz crystal A1Y2. The system clock signal (A1U6-68) is a square wave with a frequency of 921.6 kHz. It is used by the Display Assembly and the IEEE-488 option assembly after being damped by series resistor A1R57.

The Microprocessor uses synchronous communication to store and retrieve meter configuration and calibration information in the EEROM (A1U5). See the EEROM description for more detailed information.

The Microprocessor communicates to the Display Controller using a synchronous, three-wire communication interface described in detail in the Display Controller Theory of Operation.

The Microprocessor communicates to the Analog Measurement Processor (via the Serial Communication circuit) using an asynchronous communication protocol. Communication to the Analog Measurement Processor originates at A1U6-11 (which is normally low when no communication is being done). Communication from the Analog Measurement Processor to the Microprocessor appears at A1U6-10 and is normally low (unless communication is in progress.)

2-37. EEROM

The EEROM contains 64 registers, each of which is 16 bits long. These registers are used to provide non-volatile storage of meter configuration and calibration information. When the Microprocessor is communicating to the EEROM, Chip Select (A1U5-2) goes high to enable the EEROM interface.

When the Microprocessor is reading data from the EEROM, the data bits are serially shifted out on the Data Out signal (A1U5-6) with each one-to-zero transition of the Serial Clock (A1U5-3).

When the Microprocessor is writing commands and data to the EEROM, the bits are serially shifted into the EEROM on the Data In signal (A1U5-5) with each zero-to-one transition of the Serial Clock (A1U5-3). The EEROM drives the Data Out signal (A1U5-

6) low to indicate that it is busy writing the register, thereby controlling the timing of the write cycle. The microprocessor waits for this signal to go high before performing other EEROM operations. If the EEROM fails to drive this signal high, the microprocessor waits indefinitely.

New data is written to a register only after old data in that register is erased. After each such erase or write cycle, the microprocessor polls the status of EEROM by setting Chip Select (A1U5-2) high and checking the state of the Data Out signal (A1U5-6). If Data Out is low, the erase/write cycle is still in progress. If Data Out is high, the EEROM is ready for another command.

The RAM is a 8192 x 8 bit device that provides the temporary data storage used by the operating software of the meter. The chip select for this device (A1U10-20) goes low for any memory cycle between hexadecimal addresses 2000 and 3FFF. The RD* signal from the Microprocessor enables the reading of data when it is low, and the WR* signal writes data into the RAM when it is low.

The ROM provides the instruction storage for the Microprocessor. The chip select for this device (A1U8-20) goes low for any memory cycle between hexadecimal addresses 4000 and FFFF (accessing 48 kbytes.) Whenever this device is chip selected, the instruction in the addressed location is output to the data bus and read by the Microprocessor.

2-40. IEEE-488 Option Connections

The interconnection to the IEEE-488 option is implemented by two ribbon cables that mount to the 14-position and 20-position connectors on the Main PCA. The 14-position connector (A1J3) routes the 8-bit data bus, RD*, R/W*, E, RESET and OPTSW* signals to the option. The 20-position connector (A1J2) routes the 16-bit address bus and the WR* memory control signal to the option. This connector also routes the IEEE-488 interrupt and option sense signals from the option. See Chapter 8 for further information.

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