241 Display Assembly

Display Assembly operation classified into six functional circuit blocks: the Main Assembly Connector, the Front Panel Switches, the Display, the Beeper Drive Circuit, the Watchdog Timer/Reset Circuit, and the Display Controller. These blocks are described in the following paragraphs.

2-42. Main Assembly Connector

The Main Assembly Connector is a 20-pin connector (A2J1) that provides the interface between the Main Assembly and the other functional blocks on the Display Assembly. Seven of the connector pins provide the necessary connections to the four power supply voltages (-30 V dc, -5 V dc, +5 V dc, and 5 V ac). Six pins are used to provide the interface to the Front Panel Switches (A2SWR1 through A2SWR6). The other seven signals interface the Microprocessor to the Display Controller and pass the reset signals between the assemblies.

2-43. Front Panel Switches

The microprocessor scans the 19 Front Panel Switches (A2S1 through A2S18, and A2S21) using only six interface signals (plus the ground connection already available from the power supply). These six signals (SWR1 through SWR6) are connected to a bidirectional I/O port on the microprocessor. Each successive column has one less switch.

This arrangement allows the unused interface signals to function as strobe signals when their respective column is driven by the microprocessor. The microprocessor cycles through six steps to scan the complete Front Panel Switch matrix. Table 2-5 shows the interface signal state and, if the signal state is an output, the switches that may be detected as closed.

In step 1, six port bits are set to input, and the interface signal values are read. In steps 2 through 6, the bit listed as output is set to output zero, the other bits are read, and bits indicated by a Z are ignored.

Each of the interface signals is pulled up to the +5 V dc supply by a 10 kW resistor in network A2Z1. Normally, the resistance between any two of the interface signals is approximately 20 kW. Checking resistances between any two signals (SWR1 through SWR6) verifies proper termination by resistor network A2Z1.

2-44. Display

The custom vacuum-fluorescent display (A2DS1) comprises a filament, 11 grids (numbered 0 through 10 from right to left on the display), and up to 14 anodes under each grid. The anodes make up the digits and annunciators for their respective area of the display. The grids are positioned between the filament and the anodes.

The filament is driven by a 5 V ac signal that is centered on a -25 V dc level. When a grid is driven to +5 V dc, the electrons from the filament are accelerated toward the anodes that are under that grid. Anodes under that grid that are also driven to +5 V dc are illuminated, but the anodes that are driven to -30 V dc are not. Grids are sequentially driven to +5 V dc, one at a time. The sequence is from GRID(0) to GRID(10), which is right to left as the display is viewed.

2-45. Beeper Drive Circuit

The Beeper Drive circuit is controlled by U1. A 3.6-kHz square wave appears at the PPO output of U1 and across the parallel combination of A2LS1 and A2R10, causing the beeper to resonate.

Table 2-5. Front Panel Switch Scanning

Step

Interface Signal States or Key Sensed

SWR6

SWR5

SWR4

SWR3

SWR2

SWR1

1

A2S8

A2S17

A2S10

A2S12

A2S18

A2S13

2

A2S1

A2S2

A2S3

A2S4

A2S11

0

3

A2S7

A2S9

A2S5

A2S6

0

Z

4

A2S14

A2S15

A2S16

0

Z

Z

5

n/a

n/a

0

Z

Z

Z

6

A2S21

0

Z

Z

Z

Z

A2Sn indicates switch closure sensed. 0 indicates strobe driven to logic 0. Z indicates high impedance input; state ignored.

2-46. Watchdog Timer and Reset Circuit

This circuit provides active high and active low reset signals to the rest of the system at power-up or a system reset if the Microprocessor does not communicate with the Display Processor for a 5-second period. The Watchdog Timer and Reset Circuit is comprised of dual retriggerable monostable multivibrator A2U5, NAND gates from A2U6, diode A2CR3, and various resistive and capacitive timing components.

At power-up, capacitor A2C3 begins to charge up through resistor A2R3. The voltage level on A2C3 is detected by an input of Schmitt-Trigger NAND gate A2U6-12. The output of this gate (A2U6-11) then drives the active high reset signal (RESET) to the rest of the system. When the voltage on A2C3 is below the input threshold of A2U6-12, A2U6-11 is high. As soon as A2C3 charges up to the threshold of A2U6-12, A2U6-11 goes low. The RESET signal drives NAND gate inputs A2U6-1 and A2U6-2, to generate the active low reset signal (RESET*) at A2U6-3.

When the RESET signal transitions from high to low (A2U5-1), the Watchdog Timer is triggered initially, causing A2U5-13 to go high. This half of the dual retriggerable monostable multivibrator uses timing components A2R2 and A2C2 to define a nominal 4.75-second watchdog timeout period. Each time a low-to-high transition of DISTX is detected on A2U5-2, capacitor A2C2 is discharged to restart the timeout period. If there are no low-to-high transitions on DISTX during the 4.75-second period, A2U5-13 transitions from high to low, triggers the other half of A2U5, and causes output A2U5-12 to go low. A2U5-12 is then inverted by A2U6 to drive the RESET signal high, causing a system reset. The low duration of A2U5-12 is determined by timing components A2Z1 and A2C4 and is nominally 460 ^s. When A2U5-12 goes high again, RESET goes low to retrigger the Watchdog Timer.

2-47. Display Controller with FIP

The Display Controller is a 4-bit, single-chip microcomputer with high-voltage outputs that drive a vacuum-fluorescent display directly. The controller receives commands over a three-wire communication channel from the Microprocessor on the Main Assembly. Each command is transferred serially to the Display Controller on the display transmit (DISTX) signal, with bits being clocked into the Display Controller on the rising edges of the display clock signal (DSCLK). Responses from the Display Controller are sent to the Microprocessor on the display receive signal (DISRX) and are clocked out of the Display Controller on the falling edge of DSCLK.

Figure 2-9 shows the waveforms during a single command byte transfer. Note that a high DISRX signal is used to hold off further transfers until the Display Controller has processed the previously received byte of the command.

Once reset, the Display Controller performs a series of self-tests, initializing display memory and holding the DISRX signal high. After DISRX goes low, the Display Controller is ready for communication; on the first command byte from the Microprocessor, the Display Controller responds with a self-test results response. If all self-tests pass, a response of 00000001 (binary) is returned. If any self-test fails, a response of 01010101 (binary) is returned. The Display Controller initializes its display memory to one of four display patterns depending on the states of the DTEST* (A2U1-41) and LTE* (A2U1-13) inputs. The DTEST* input is pulled up by A2Z1, but may be pulled down by jumpering A2TP4 to A2TP3 (GND). The LTE* input is pulled down by A2R12, but may be pulled up by jumpering A2TP5 to A2TP6 (VCC). The default conditions of DTEST* and LTE* cause the Display Controller to turn all segments on bright at power-up.

Table 2-6 defines the logic and the selection process for the four display initialization modes.

The two display test patterns are a mixture of on and off segments forming a recognizable pattern that allows for simple testing of display operation. The Display Controller provides 10 grid control outputs and 14 anode control outputs. Each of these 24 highvoltage outputs provides an active driver to the +5 V dc supply and a passive 70 kW

(nominal) pull-down to the -30 V dc supply. These pull-downs are internal to the Display Controller.

The output port, P63, of the Display Controller, is used as a grid control output for GRID(10), of the vacuum-fluorescent display. A high voltage output, from P63, is provided with a 10 kW resistor (A2R1), and PNP transistor (A2Q1) provide an active driver to the +5 V dc supply and a passive 47 kW pull-down (A2R4) to -30 V dc.

The Display Controller drives the vacuum-fluorescent display in a multiplexed manner by strobing each grid individually while the segment data for that display area is presented on the anode outputs. Each grid is strobed for approximately 427 microseconds every 5.368 milliseconds, resulting in each grid on the display being strobed about 170 times per second. The grid strobing sequence is from GRID(0) to GRID(10), which results in right-to-left strobing of grid areas on the display. Figure 2-10 shows grid control signal timing.

The single grid strobing process involves turning off the previously enabled grid, outputting the anode data for the next grid, and then enabling the next grid. This procedure ensures that there is some time between grid strobes so that no shadowing occurs on the display. Figure 2-11 describes the timing relationship between an individual grid control signal and the anode control signals.

qb09.eps

Figure 2-9. Command Byte Transfer Waveforms qb09.eps

Figure 2-9. Command Byte Transfer Waveforms

Table 2-6. Display Initialization Modes

A2TP4 Dtest*

A2TP5 LTE*

Power-Up Display Initialization

1

1

All Segments OFF

1

0

All Segments ON (default)

0

1

Display Test Pattern #1

0

0

Display Test Pattern #2

qb10f.eps

Figure 2-10. Grid Control Signal Timing qb10f.eps

Figure 2-10. Grid Control Signal Timing

Grid/Anode Timing

Grid/Anode Timing

5V 0V

-30V

qb11f.eps

Figure 2-11. Grid-Anode Timing Relationships

A

static awareness

A

L

i

A

Some semiconductors and custom IC's can be damaged by electrostatic discharge during handling. This notice explains how you can minimize the chances of destroying such devices by:

1. Knowing that there is a problem.

2. Leaning the guidelines for handling them.

3. Using the procedures, packaging, and bench techniques that are recommended.

The following practices should be followed to minimize damage to S.S. (static sensitive) devices.

1. MINIMIZE HANDLING

1. MINIMIZE HANDLING

3. DISCHARGE PERSONAL STATIC BEFORE HANDLING DEVICES. USE A HIGH RESISTANCE GROUNDING WRIST STRAP.

4. HANDLE S.S. DEVICES BY THE BODY.

2. KEEP PARTS IN ORIGINAL CONTAINERS UNTIL READY FOR USE.

4. HANDLE S.S. DEVICES BY THE BODY.

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5. USE STATIC SHIELDING CONTAINERS FOR HANDLING AND TRANSPORT.

8. WHEN REMOVING PLUG-IN ASSEMBLIES HANDLE ONLY BY NON-CONDUCTIVE EDGES AND NEVER TOUCH OPEN EDGE CONNECTOR EXCEPT AT STATIC-FREE WORK STATION. PLACING SHORTING STRIPS ON EDGE CONNECTOR HELPS PROTECT INSTALLED S.S. DEVICES.

6. DO NOT SLIDE S.S. DEVICES OVER ANY SURFACE.

9. HANDLE S.S. DEVICES ONLY AT A STATIC-FREE WORK STATION.

10. ONLY ANTI-STATIC TYPE SOLDER-SUCKERS SHOULD BE USED.

11. ONLY GROUNDED-TIP SOLDERING IRONS SHOULD BE USED.

7. AVOID PLASTIC,VINYL AND STYROFOAM® IN WORK AREA.

PORTIONS REPRINTED

WITH PERMISSION FROM TEKTRONIX INC.

AND GERNER DYNAMICS, POMONA DIV.

® Dow Chemical

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