515 Display Assembly Troubleshooting

The following discussion is helpful if it has been determined that the Display Assembly is faulty. This initial determination may not be arrived at easily, since an improperly operating display may be the result of a hardware or software problem that is not a direct functional part of the Display Assembly. Consult the General Troubleshooting Procedures found earlier in this chapter for procedures to isolate the fault to the Display Assembly. Use the following discussion of display software operation when troubleshooting problems within a known faulty Display Assembly. A Display Extender Cable is available (PN 867952) for use during troubleshooting.

Figure 5-4 shows the timing of communications between the main processor and the display controller.

The Display Controller reads the DTEST* and LTE* inputs to determine how to initialize the display memory. DTEST* and LTE* default to logic 1 and logic 0, respectively, to cause all display segments to be initialized to "on". DTEST* is connected to test points A2TP4, and LTE* is connected to A2TP5. Either test point can be jumpered to VCC (A2TP6) or GND (A2TP3) to select other display initialization patterns. Display Test Patterns #1 and #2 are a mixture of "on" and "off" segments with a recognizable pattern to aid in troubleshooting problems involving individual display segments. When either of the special display patterns is selected, the beeper is also sounded for testing without interaction with the main processor. Table 5-5 indicates the display initialization possibilities. Figures 5-5 and 5-6 show grid and anode assignments for primary and secondary displays, respectively.


Figure 5-4. Display Controller to Microprocessor Signals qb09.eps

Figure 5-4. Display Controller to Microprocessor Signals

Table 5-5. Display Initialization

A2TP4 Dtest*


Power-Up Display Initialization



All Segments OFF



All Segments ON (default)



Display Test Pattern #1



Display Test Pattern #2


Figure 5-5. Primary Display

Display A2ds1
Figure 5-6. Secondary Display

When a Fluke 45 display is initially powered up, all display segments should come on automatically. If this display does not appear, proceed with the following steps:


If the display is operational but has problems with front-panel button presses, proceed directly to step 9.

1. Check the three power supplies with respect to GND (A2TP3 or A2U1-42) on the Display Assembly.

2. Check the filament drive signals FIL1 and FIL2; these connect to the last two pins on each end of A2DS1. These signals should be 5.0 V ac centered on a -25 V dc level. FIL1 and FIL2 should be 180 degrees out of phase. If the dc bias of the filament signals is not at about -25 V dc, the display segments that should be "off" will show a shadowing (or speckling) effect.


It may be necessary to disable the watchdog reset by jumpering A2TP1 (A1U5-3, A1U5-11) to GND (A2TP3) to verify the following items.

3. Check the clock signal at A2TP2. This signal should be 4.19 MHz (.238 ^s per cycle).

If the signal is not 4.19 MHz, the ceramic resonator, U2 is probably defective.

4. Check the state of the RESET signal (A2U1-1). This signal should be low once the reset time is completed (after power-up).

5. Verify that the DISRX signal (A2U1-39) goes low after RESET (A2U1-1) goes low. If this sequence does not occur, communication to the Main Processor is held off with the DISRX signal high. If DISRX stays high but is not shorted to VCC, A2U1 must be faulty.

6. Verify activity for both the DISTX and DSCLK signals. These signals are driven by the Main Processor and must be transitioning for the Display Controller to receive commands from the Main Processor.

7. If all segments of a particular digit do not turn on at power-up, the grid drive from A2U1 may not be connected properly to A2DS1. Grids are numbered from 0 to 10 (left to right as the display is viewed). For a digit to be enabled, the respective grid drive signals (GRID(0:10)) must be at approximately VCC (4.85 to 5.35 V dc.) For a digit to be disabled, the drive must be at VLOAD (-28.5 to -32.0 V dc.)

8. If a segment under each of several (or all) grids fails to be turned on (or off) properly, one of the anode drive signals may not be connected properly from A2U1 to A2DS1. When an anode signal is at VCC, and a grid signal is at VCC, then the corresponding segment on the display is illuminated.

9. If the Main Processor has difficulty recognizing front-panel button presses, the switch scanning signals (SWR1 through SWR6, A1U6-21 through -26, respectively) should be checked. When no switch contacts are being closed, the switch scanning lines should have about 20 kW of resistance between each other (through two 10 kW pullup resistors to VCC). None of the switch scanning lines should be shorted directly to GND at any time, unless one of the switches is closed.

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