Power supply, battery charger LCD back light voltage converter Optical interface input
All circuits, except the LCD unit and the KEYBOARD, are located on one Printed Circuit Board (PCB), called the MAIN PCB.
The ASIC's are referred to as C-ASIC (Channel ASIC), T-ASIC (Trigger ASIC), P-ASIC (Power ASIC), and D-ASIC (Digital ASIC).
3.2.1 Channel A, Channel B Measurement Circuits
The Channel A and Channel B circuit are similar. The only difference is that Channel A can do all measurements, whereas Channel B does not provide resistance, diode, and capacitance measurements.
Volts, and derived measurements (e.g. current with optional probe)
The input voltage is supplied to the C-ASIC, via the LF and HF path. The C-ASIC converts (attenuates, amplifies) the input signal to a normalized output voltage ADC-A/ADC-B, which is supplied to the Analog to Digital Converters (ADC-A and ADC-B) on the DIGITAL part. The D-ASIC acquires the digital samples to build the trace, and to calculate readings. For the HF and LF attenuation section of the C-ASIC some external components are required: the HF DECade ATTenuator and LF DECade ATTenuator section.
Resistance, continuity, and diode measurements (Input A only)
The T-ASIC supplies a current via the Q/F relays to the unknown resistance Rx, connected to the Input A and the COM input jacket. The voltage drop across Rx is measured as for voltage measurements.
Capacitance measurements (Input A only)
The T-ASIC supplies a current via the Q/F relays to the unknown capacitance Cx, connected to the Input A and the COM input jacket. Cx is charged and discharged by this current. The C-ASIC converts the charging time and the discharging time into a pulse width signal. This signal is supplied to the T-ASIC via the C-ASIC trigger output TRIG-A. The T-ASIC shapes and levels the signal, and supplies the resulting pulse width signal ALLTRIG to the D-ASIC. The D-ASIC counts the pulse width and calculates the capacitance reading.
When the capacitance function is selected no other measurement or wave form display is possible. There is only a numeric readout of the capacitance value.
Frequency, pulse width, and duty cycle measurements
The input voltage is measured as described above. From the ADC samples to built the trace, also the frequency, pulse width, and duty cycle of the input signal are calculated.
Control of the C-ASIC, e.g. selecting the attenuation factor, is done by the D-ASIC via the SDAT and SCLK serial communication lines.
An offset compensation voltage and a trace position control voltage are provided by the D-ASIC via the APWM bus.
The C-ASIC's also provide conditioned input voltages on the TRIG-A/TRIG-B line. These voltages can be selected as trigger source by the T-ASIC.
The T ASIC selects one of the possible trigger sources TRIG-A (Input A) or TRIG-B (Input B). For TV triggering the selected trigger source signal is processed via the Sync(hronization) Pulse Separator circuit (TVOUT-TVSYNC lines). Two adjustable trigger levels are supplied by the D-ASIC via the PWM FILTERS (TRIGLEV1 and TRIGLEV2 line). Depending on the selected trigger conditions (- source, - level, - edge, - mode), the T-ASIC generates the final trigger signal TRIGDT, which is supplied to the D-ASIC.
External triggers, supplied via the optical interface RXDA line, are buffered by the P-ASIC, and then supplied to the D-ASIC (RXD signal).
The TRIG-A input is also used for capacitance measurements, as described in Section 3.2.1.
The T-ASIC includes a constant current source for resistance and capacitance measurements. The current is supplied via the GENOUT output and the Q/F relays to the unknown resistance Rx or capacitance Cx connected to Input A. The SENSE signal senses the voltage across Cx and controls a CLAMP circuit in the T-ASIC. This circuit limits the voltage on Input A at capacitance measurements. The protection circuit prevents the T-ASIC from being damaged by voltages supplied to the input during resistance or capacitance measurements.
For probe adjustment, a voltage generator circuit in the T-ASIC can provide a square wave voltage via the GENOUT output to the Input A connector.
The T-ASIC contains opamps to derive reference voltages from a 1.23 V reference source. The gain factors for these opamps are determined by resistors in the REF GAIN circuit. The reference voltages are supplied to various circuits.
The T-ASIC also controls the Channel A and B AC/DC input coupling relays, and the Q/F relays.
Control data for the T-ASIC are provided by the D-ASIC via the SDAT and SCLK serial communication lines.
The D-ASIC includes a micro processor, ADC sample acquisition logic, trigger processing logic, display and keyboard control logic, I/O ports, and various other logic circuits.
The instrument software is stored in the FlashROM, the RAM is used for temporary data storage. The RESET ROM circuit controls the operating mode of the FlashROM (reset, programmable, operational).
For Voltage and Resistance measurements, the conditioned Input A/ Input B voltages are supplied to the ADC-A and ADC-B ADC. The voltages are sampled, and digitized by the ADC's. The output data of the ADC's are acquired and processed by the D-ASIC. For capacitance measurements, the ALLTRIG signal generated by the T-ASIC, is used. The D-ASIC counts the ALLTRIG signal pulse width, which is proportional to the unknown capacitance.
The DPWM-BUS (Digital Pulse Width Modulation) supplies square wave signals with a variable duty cycle to the PWM FILTERS circuit (RC filters). The outgoing APWM-BUS (Analog PWM) provides analog signals of which the amplitude is controlled by the D-ASIC. These voltages are used to control e.g. the trace positions (C-ASIC), the trigger levels (T-ASIC), and the battery charge current (P-ASIC).
In random sampling mode (time base faster than 1 ^s/div.), a trace is built-up from several acquisition cycles. During each acquisition, a number of trace samples are placed as pixels in the LCD. The RANDOMIZE circuit takes care that the starting moment of each acquisition cycle (trigger release signal HOLDOFF goes low) is random. This prevents that at each next acquisition the trace is sampled at the same time positions, and that the displayed trace misses samples at some places on the LCD.
The D-ASIC supplies control data and display data to the LCD module. The LCD module is connected to the main board via connector X453. It consists of the LCD, LCD
drivers, and a fluorescent back light lamp. As the module is not repairable, no detailed description and diagrams are provided. The back light supply voltage is generated by the back light converter on the POWER part.
The keys of the keyboard are arranged in a matrix. The D-ASIC drives the rows and scans the matrix. The contact pads on the keyboard foil are connected to the main board via connector X452. The ON-OFF key is not included in the matrix, but is sensed by a logic circuit in the D-ASIC, that is active even when the test tool is turned off.
Via the PROBE-A and PROBE-B lines, connected to the Input A and Input B banana shielding, the D-ASIC can detect if a probe is connected. This function is not supported by the Fluke 123 software.
The D-ASIC sends commands to the C-ASICs and T-ASIC via the SCLK and SDAT serial control lines, e.g. to select the required trigger source.
Various I/O lines are provided, e.g. to control the BUZZER and the Slow-ADC (via the SADC bus.
The test tool can be powered via the power adapter, or by the battery pack. If the power adapter is connected, it powers the test tool and charges the battery via the CHARGER-CONVERTER circuit. The battery charge current is sensed by sense resistor Rs (signal IBAT). It is controlled by changing the output current of the CHARGER-CONVERTER (control signal CHAGATE).
If no power adapter is connected, the battery pack supplies the VBAT voltage. The VBAT voltage powers the P-ASIC, and is also supplied to the FLY BACK CONVERTER (switched mode power supply).
If the test tool is turned on, the FLY BACK CONVERTER generates supply voltages for various test tool circuits.
The +3V3GAR supply voltage powers the D-ASIC, RAM and ROM. If the test tool is turned off, the battery supplies the +3V3GAR voltage via transistor V569. This transistor is controlled by the P-ASIC. So when the test tool is turned off, the D-ASIC can still control the battery charging process (CHARCURR signal), the real time clock, the on/off key, and the serial RS232 interface (to turn the test tool on).
To monitor and control the battery charging process, the P-ASIC senses and buffers various battery signals, as e.g. temperature (TEMP), voltage (BATVOLT), current (IBAT).
Via the SLOW ADC various analog signals can be measured by the D-ASIC. Involved signals are: battery voltage (BATVOLT), battery type (IDENT), battery temperature (TEMP), battery current (BATCUR) LCD temperature (LCDTEMP, from LCD unit), and 3 test output pins of the C-ASIC's, and the T-ASIC (DACTEST). The signals are used for control and test purposes.
The BACK LIGHT CONVERTER generates the 400V ! supply voltage for the LCD fluorescent back light lamp. If the lamp is defective a 1.5 kV voltage can be present for 0.2 second maximum. The brightness is controlled by the BACKBRIG signal supplied by the D-ASIC.
Serial communication with a PC or printer is possible via the RS232 optically isolated interface. This interface is also used for external trigger input using the Isolated Trigger Probe. The P-ASIC buffers the received data line (RXDA) and supplies the buffered data (RXD) to the D-ASIC. The transmit data line TXD is directly connected to the D-ASIC.
A linear regulator in the P-ASIC derives a +12V voltage from the power adapter voltage.
The +12V is used as programming voltage for the Flash EPROM on the Digital part.
3.2.5 Start-up Sequence, Operating Modes
The test tool sequences through the following steps when power is applied (see also
1. The P-ASIC is directly powered by the battery or power adapter voltage VBAT. Initially the Fly Back Converter is off, and the D-ASIC is powered by VBAT via transistor V569 (+3V3GAR).
If the voltage +3V3GAR is below 3.05 V, the P-ASIC keeps its output signal VGARVAL (supplied to the D-ASIC) low, and the D-ASIC will not start up. The test tool is not working, and is in the Idle mode.
2. If the voltage +3V3GAR is above 3.05 V, the P-ASIC makes the line VGARVAL high, and the D-ASIC will start up. The test tool is operative now. If it is powered by batteries only, and not turned on, it is in the Off mode. In this mode the D-ASIC is active: the real time clock runs, and the ON/OFF key is monitored to see if the test tool will be turned on.
3. If the power adapter is connected (P-ASIC output MAINVAL high), and/or the test tool is turned on, the embedded D-ASIC program, called mask software, starts up. The mask software checks if valid instrument software is present in the Flash ROM's. If not, the test tool does not start up and the mask software continues running until the test tool is turned off, or the power is removed. This is called the Mask active mode. The mask active mode can also be entered by pressing the A and > key when turning on the test tool.
If valid instrument software is present, one of the following modes will become active:
The Charge mode is entered when the test tool is powered by the power adapter, and is turned off. The FLY-BACK CONVERTER is off. The CHARGER-CONVERTER charges the batteries (if installed).
Operational & Charge mode
The Operational & Charge mode is entered when the test tool is powered by the power adapter, and is turned on. The FLY-BACK CONVERTER is on, the CHARGER-CONVERTER supplies the primary current. If batteries are installed, they will be charged. In this mode a battery refresh (see below) can be done.
The Operational mode is entered when the test tool is powered by batteries only, and is turned on. The FLY-BACK CONVERTER is on, the batteries supply the primary current. If the battery voltage (VBAT) drops below 4V when starting up the fly back converter, the Off mode is entered.
In the following situations the batteries will need a deep discharge-full charge cycle, called a "refresh":
• every 50 not-full discharge/charge cycles, or each 6 months. This prevents battery capacity loss due to the memory effect.
• after the battery has been removed, as the test tool does not know the battery status then.
The user will be prompted for this action when he turns the test tool on, directly following the start up screen. A refresh cycle takes 16 hours maximum, depending on the battery status. It can be started via the keyboard (USER OPTIONS, F1, activate refresh) if the test tool is on, and the power adapter is connected. During a refresh, first the battery is completely charged, then it is completely discharged (the test tool is powered by the battery only, and the power adapter must be connected!), and then it is completely charged again.
Table 3-2 shows an overview of the test tool operating modes.
No power adapter and no battery
No power adapter connected, battery installed, test tool off
P-ASIC & D-ASIC powered (VBAT & +3V3GAR).
Mask active mode
No valid instrument software, or A and > key pressed when turning on
Mask software runs
Power adapter connected and test tool off
Batteries will be charged
Operational & Charge mode
Power adapter connected and test tool on
Test tool operational, and batteries will be charged
No power adapter connected, battery installed, and test tool on
Test tool operational, powered by batteries
3.3 Detailed Circuit Descriptions
3.3.1 Power Circuit
The description below refers to circuit diagram Figure 9-5.
Power Sources , Operating Modes
Figure 3-3 shows a simplified diagram of the power supply and battery charger circuit.
As described in Section 3.2.5, the test tool operating mode depends on the connected power source.
The voltage VBAT is supplied either by the power adapter via V506/L501, or by the battery pack. It powers a part of the P-ASIC via R503 to pin 60 (VBATSUP). If the test tool is off, the Fly Back Converter is off, and VBAT powers the D-ASIC via transistor V569 (+3V3GAR). This +3V3GAR voltage is controlled and sensed by the P-ASIC. If it is NOT OK (<3.05V), the output VGARVAL (pin 64) is low. The VGARVAL line is connected to the D-ASIC, and if the line is low, the D-ASIC is inactive: the test tool is in the Idle mode. A low VGARVAL line operates as a reset for the D-ASIC.
If VGARVAL is high (+3V3GAR > 3.05V), the D-ASIC becomes active, and the Off mode is entered. The D-ASIC monitors the P-ASIC output pin 12 MAINVAL, and the test tool ON/OFF status. By pressing the ON/OFF key, a bit in the D-ASIC, indicating the test tool ON/OFF status is toggled. If neither a correct power adapter voltage is supplied (MAINVAL is low), or the test tool is turned on, the Off mode will be maintained.
If a correct power adapter voltage is supplied (MAINVAL high), or if the test tool is turned on, the mask software starts up. The mask software checks if valid instrument software is present. If not, e.g. no instrument firmware is loaded, the mask software will keep running, and the test tool is not operative: the test tool is in the Mask active state. For test purposes the mask active mode can also be entered by pressing the A and > key when the test tool is turned on.
If valid software is present, one of the three modes Operational, Operational & Charge or Charge will become active. The Charger/Converter circuit is active in the Operational & Charge and in the Charge mode. The Fly back converter is active in the Operational and in the Operational & Charge mode.
Charger/Converter (See Also Figure 3-3.)
The power adapter powers the Charge Control circuit in the P-ASIC via an internal linear regulator. The power adapter voltage is applied to R501. The Charger/Converter circuit controls the battery charge current. If a charged battery pack is installed, VBAT is approximately +4.8V. If no battery pack is installed, VBAT is approximately +15V. The voltage VBAT is supplied to the battery pack, to the P-ASIC, to the Fly Back Converter, and to transistor V569. The FET control signal CHAGATE is a 100 kHz square wave voltage with a variable duty cycle , supplied by the P-ASIC Control circuit. The duty cycle determines the amount of energy loaded into L501/C503. By controlling the voltage VBAT, the battery charge current can be controlled. The various test tool circuits are supplied by the Fly Back Converter, and/or V569.
The P-ASIC supplies a current to reference resistor R516 (VADALOW pin 8). It compares the voltage on R516 to the power adapter voltage VADAPTER on pin 20 (supplied via R502, and attenuated in the P-ASIC). If the power adapter voltage is below 10V, the P-ASIC output pin 12, and the line MAINVAL, are low. This signal on pin 12 is also supplied to the P-ASIC internal control circuit, which then makes the CHAGATE signal high. As a result FET V506 becomes non-conductive, and the Charger/Converter is off.
The actual charge current is sensed via resistors R504-R506-507, and filter R509-C509, on pin 9 of the P-ASIC (IBATP). The sense voltage is supplied to the control circuit. The required charge current information is supplied by the D-ASIC via the CHARCUR
line and filter R534-C534 to pin 80. A control loop in the control circuit adjusts the actual charge current to the required value.
The filtered CHARCUR voltage range on pin 80 is 0... 2.7V for a charge current from 0.5A to zero. A voltage of 0V complies to 0.5A (fast charge), 1.5 V to 0.2A (top off charge), 2.3V to 0.06A (trickle charge), and 2.7V to 0A (no charge). If the voltage is > 3 Volt, the charger converter is off (V506 permanently non-conductive).
The D-ASIC derives the required charge current value from the battery voltage VBAT. The P-ASIC converts this voltage to an appropriate level and supplies it to output pin 78 (BATVOLT). The D-ASIC measures this voltage via the Slow ADC. The momentary value, and the voltage change as a function of time (-dV/dt), are used as control parameters.
If the battery voltage drops below 5.2V, and the battery temperature is between 10 and 45°C, the charge current is set to 0.5A (fast charge). From the battery voltage change -dV/dt the D-ASIC can see when the battery is fully charged, and stop fast charge. Additionally a timer in the D-ASIC limits the fast charge time to 6 hours. After fast charge, a 0.2A top off charge current is supplied for 2 hours. Then a 0.06A trickle charge current is applied for 48 hours maximum. If the battery temperature becomes higher than 50°C, the charge current is set to zero
The P-ASIC supplies a current to a NTC resistor in the battery pack (TEMP pin 5). It conditions the voltage on pin 5 and supplies it to output pin 79 BATTEMP. The D-ASIC measures this voltage via the slow ADC. It uses the BATTEMP voltage to decide if fast charge is allowed (10-45°C), or no charge is allowed at all (<10°C, >50°C).
Additionally the temperature is monitored by the P-ASIC. The P-ASIC supplies a current to reference resistor R512 (TEMPHI pin 4), and compares the resulting TEMPHI voltage to the voltage on pin 5 (TEMP). If the battery temperature is too high, the P-ASIC Control circuit will set the charge current to zero, in case the D-ASIC fails to do this.
If the battery temperature monitoring system fails, a bimetal switch in the battery pack interrupts the battery current if the temperature becomes higher then 70 °C
The P-ASIC supplies a current to reference resistor R513 (VBATHIGH pin 7). It compares the voltage on R513 to the battery voltage VBAT on pin 3 (after being attenuated in the P-ASIC). The P-ASIC limits the voltage VBAT to 7.4V via its internal Control circuit. This situation arises in case no battery or a defective battery (open) is present.
Charger/Converter input current
This input current is sensed by R501. The P-ASIC supplies a reference current to R514. The P-ASIC compares the voltage drop on R501 (CHASENSP-CHASENSN pin 14 and 15) to the voltage on R514 (IMAXCHA pin 6). It limits the input current (e.g. when loading C503 and C555 just after connecting the power adapter) via its internal Control circuit.
To make the FET conductive its Vgs (gate-source voltage) must be negative. For that purpose, the CHAGATE voltage must be negative with respect to VCHDRIVE. The P-ASIC voltage VCHDRIVE also limits the swing of the CHAGATE signal to 13V.
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