0037

Thus for this case, a 10 percent power-supply voltage change results in a 0.37 percent change in out- The result is significantly better than for a bipolar Widlar current source. The MOS counterpart of the base-emitter reference is shown in Fig. 4.366. Here The case of primary interest is when the overdrive of T is small compared to the threshold voltage. This case can be achieved in practice by choosing sufficiently low input current and large (W L)i. In this case, the output current is...

0045

These circuits are not fully supply independent because the base-emitter or gate-source voltages of T change slightly with power-supply voltage. This change occurs because the collector or drain current of T is approximately proportional to the supply voltage. The resulting supply sensitivity is often a problem in bias circuits whose input current is derived from a resistor connected to the supply terminal, since this configuration causes the currents in some portion of the circuit to change...

03

04 06 > 04 13 13 13 13 13 14 2 mic 2 cmosn 2 m2c 2 cmosn 04 1.023e-04 15 -4.594e-15 14 -1.1121-14 01 7.754e-01 01 6.5231-01 01 -4.5941-01 01 6.656b-01 9.5631-02 1.912e-02 5.2181-01 1.820e-03 3.0761-05 4.081e-04 5.1721-14 1.592e-13 1.716e-13 6.4531-14 1.3661-13 2.240e-14 xcm 2 m3 2 cm0sp -1.0231-04 1.548e-20 2.1881-14 -9.912e-01 -2.1881+00 0. -7.733e-01 -1.875e-01 4.9781-03 4.909e-01 9.2251-04 1.936e-06 2.6711-04 9.103e-14 4.0461-13 4.639e-13 1.511e-13 3.7061-13 3.360e-14 -1.0231-04 -1.000e-04...

1

The validity of (1.51) depends on W2Bl2TbDn 1 and (Dp Dn)(WB Lp)(NA ND) < sc 1, and this is always true if 3F is large see (1.48) . The term y in (1.51) is called the emitter injection efficiency and is equal to the ratio of the electron current (npn transistor) injected into the base from the emitter to the total hole and electron current crossing the base-emitter junction. Ideally y 1, and this is achieved by making ND NA large and WB small. In that case very little reverse injection occurs...

1 1 1

Figure 9.45 Poles of the transfer function of the feedback amplifier of Fig. 9.41. The transfer function contains no zeros. near the jco axis, which would give rise to an excessively peaked response. In practice, oscillation can occur because higher magnitude poles do exist and these would tend to give a locus of the kind of Fig. 9.39, where the remote poles cause the locus to bend and enter the right half-plane. (Note that this behavior is consistent with the alternative approach of...

1 1 1 jsiIsO JVApF49

The first term in (4.9) stems from finite output resistance and the second term from finite If Vce2 > Vcei the polarities of the two terms are opposite. Since the two terms are independent, however, cancellation is unlikely in practice. The first term dominates when the difference in the collector-emitter voltages and 3p are large. For example, with identical transistors and VA 130 V, if the collector-emitter voltage of Q is held at vbe (on), and if the collector-emitter voltage of q2 is 30...

1 1

Another way to arrive at this estimate of p is to apply the Miller effect to Cmi- The effective Miller capacitor is about Cm2 times the negative of the gain across Cm2, which is gmiRxgmiRi- This capacitor appears in parallel with Rq, giving a time constant of The other poles P2 and could be found by factoring the third-order denominator in (9.56), which can be done using a computer but is difficult by hand. However, these poles can be estimated from a quadratic equation under certain...

10

VOLT Vi 5' 1A > -2.CC0E+C0 -1.0001-00 V. 5C0E-C-l 7.610E-01 7.62GE-01 7.630E-01 7.6 0E-01 7 .6501-01 7.660E-01 7.670E-01 7.580E-01 7.690E-01 1-7001-01 7.710E-01 7.7201-01 7.730E-01 7.7 0E-01 7.75CE-01 7.760E-01 7.7705-01 7.730E-01 7.7901-01 7.SOOE-OI 1.8101-01 7.S20E-01 7.B30E-01 7.8401-01 7.8502-01 7.860E-01 7.870E-01 7.5801-01 7 390E-31 7.900E-01 1.05E+QO-1.05E+00 1.05E.G0 1.05E+00 1.05E+00 1.05E+00 1.0IE+00 1.04E+00 1.0 E+00 1.03E+00 1.03E+00-8.B9E-01 7.03E-01 5.251-01 3.56E-01 2.00E-01...

10 V

Figure 11.54 Differential-pair input stage for Problem 11.14. figure of this circuit in decibels for 10 kft using the following data. Neglect flicker noise and capacitive effects. (b) If the device has fT 500 MHz, calculate the frequency where the noise figure is 3 dB above its low-frequency value. 11.20 (a) Neglecting capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.52 with Rs 5 kft. Use data as in Problem 11.10. (b) If the flicker noise corner frequency for...

1000

V0(t) 0.031 sin (27t x 102r) - 51 Operating the loop with no loop filter has several practical drawbacks. Since the phase detector is really a multiplier, it produces a sum frequency component at its output as well as the difference frequency component. This component at twice the carrier frequency will be fed directly to the output if there is no loop filter. Also, all the out-of-band interfering signals present at the input will appear, shifted in frequency, at the output. Thus, a loop filter...

1000102

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102 Precision Rectification

Perhaps the most basic nonlinear operation performed on time-varying signals is rectification. An ideal half-wave rectifier is a circuit that passes signal currents or voltages of only one polarity while blocking signal voltages or currents of the other polarity. The transfer characteristic of an ideal half-wave rectifier is shown in Fig. 10.1. Also shown in Fig. 10.1 is the transfer characteristic of a second useful rectifier, the full-wave type. Practical rectifiers can be divided into two...

1035 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector

The four-quadrant multiplier just described is an example of an application of the multiplier cell in which all the devices remain in the active region during normal operation. Used in this way the circuit is capable of performing precise multiplication of one continuously varying analog signal by another. In communications systems, however, the need frequently arises for the multiplication of a continuously varying signal by a square wave. This is easily accomplished with the multiplier...

1041 Phase Locked Loop Concepts

A block diagram of the basic phase-locked loop system is shown in Fig. 10.18. The elements of the system are a phase comparator, a loop filter, an amplifier, and a voltage-controlled oscillator. The voltage-controlled oscillator, or VCO, is simply an oscillator whose frequency is proportional to an externally applied voltage. When the loop is locked on an incoming periodic signal, the VCO frequency is exactly equal to that of the incoming signal. The phase detector produces a dc or...

1042 The Phase Locked Loop in the Locked Condition

Under locked conditions, a linear relationship exists between the output voltage of the phase detector and the phase difference between the VCO and the incoming signal. This fact allows the loop to be analyzed using standard linear feedback concepts when in the locked condition. A block diagram representation of the system in this mode is shown in Fig. 10.20. The gain of the phase comparator is KD V rad of phase difference, the loopfilter transfer function is F(s), and any gain in the forward...

12

To find em, we will again refer to Fig. 4.266 with v,i vt2 vic. In writing (4.134), we assumed that l gm3. We will now reconsider this assumption and write We will still assume that the two transistors in the differential pair match perfectly and operate with equal dc currents, as do the two transistors in the active load. Then (4.174) can be rewritten as Mmir) + 2i0(m(> ) + gm mir) rrr(mir)fo(mir) Substituting (4.175) into (4.135) gives rTr(mir) I 2r0(mir) gm mir)rir(mir)roimir) Substituting...

12 V

Figure 5.42 k -npn Darlington output stage. (c) Calculate the maximum average power that can be delivered to RL 8 ft before clipping occurs and the corresponding efficiency of the complete circuit. Also calculate the maximum instantaneous power dissipated in each output transistor. Assume that feedback is used around the circuit so that V0 is approximately sinusoidal. (d) Use SPICE to plot the dc transfer characteristic from Vj to V as V0 is varied over the complete output voltage range with RL...

1258806 1511806 1395806

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130

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131

CK 1.449E-13 1.70 E-13 1.7068-13 1.449E-13 CCS 5.7951-13 7.359E-13 7.3591-13 5.795E-13 BETMC 2.000E+02 2.000E+02 2.000E+02 2.000E+02 PT 7.747E+06 2.071E+08 2.071E+08 7.747E+06 IC HttLTSIS THOH 27.000 TEUF* 27.000 (A I -2.0008*01 0. 2.000B*01 1.0008*01 6.000E 01 9.9998*03 3 1.2581*0 3.798*01 ****** A*** 1.5818*0 3.798*01 ****** A*** 1.9958*0 3.798*01 ** A 2.5118*01 3.798*01 ****** A + * 3.9818*01 3 .798*01 ****** A+* 5.0118*0 3.798*01 ****** A* + * 6.3098*0 3.798*01 ****** A*** 1.0008*05...

136 058

Similar calculations show that the parameters of Q3 are 0.20 pF and Ccs3 0.35 pF. The -3-dB frequency of the circuit can now be estimated by calculating the zero-value time constants for the circuit. First consider C i. The resistance seen across its terminals is given by (7.122), which was derived for the emitter follower. The presence of resistance in series with the collector of Q makes no difference to the calculation because of the infinite impedance of the current generator gm Vi. Thus...

14

Also, (W L)21 14 since M26 and M27 are matched. In the example in Section 9.4.3, a compensation capacitor of 3.2 pF provided a 45 phase margin for a feedback factor of unity and a 5-pF load. The DM half-circuits for this example with the independent voltage sources Vsi and Vs2 set to zero are shown in Fig. 12.21 a. Here, we have assumed that CL is much larger than the input capacitance of the CM-sense devices M21 -M2a The two feedback networks connect between the two half-circuits in this...

15 V

Figure 9.59 Input stages of an op amp. 9.25 Assuming that the zero has been moved to infinity, determine the maximum load capacitance that can be attached directly to the output of the circuit of Fig. 9.60 and still maintain a phase margin of 45 . Neglect all higher order poles except any due to the load capacitance. Use the value of W L obtained in Problem 9.23 for M9 with the bias circuit of Fig. 9.61. 9.26 Repeat Problem 9.25 except, for the op amp, use the aspect ratios, supply voltages,...

16

Die in integrated high-frequency communication circuits. There are no sources of noise in ideal capacitors or inductors. In practice, real components have parasitic resistance that does display noise as given by the thermal noise formulas of (11.4) and (11.5). In the case of integrated-circuit capacitors, the parasitic resistance usually consists of a small value in series with the capacitor. Parasitic resistance in inductors can be modeled by either series or shunt elements. The device...

169

We will now calculate rc2, assuming a buried-layer sheet resistance of 20 ft Q The distance from the center of the emitter to the center of the collector-contact diffusion is 62 xm, and the width of the buried layer is 41 fxm. The rc2 component is thus, approximately, Here the buried-layer side diffusion was not taken into account because the ohmic resistance of the buried layer is determined entirely by the number of impurity atoms actually diffused see (2.15) into the silicon, which is...

17

Figure 5.35 Schematic of the top error amplifier and output transistor M Figure 5.35 Schematic of the top error amplifier and output transistor M Since Mi3 and Mu also form a current mirror, and since (W L) 4 (W L) 13, Substituting (5.131) and (5.132) into (5.133) gives , _ , (w l) 13 tail hie - 'bias + Since ID15 di6 when IDU )12, KSD14 VsDn (313 V gl Therefore, ignoring channel-length modulation, Substituting (5.130) into (5.136) and rearranging gives

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2 8 2

for n-chab, 1 - ot*cox 550*1.38e-7 127 ba v**2 for f-chaff, KP dp'cox 250*1.3 e-7 58 oa v**2 . del mos mos level-1 lambda-o.105263 vto-0.7 kp-127u ld-0.12 model pmos pmos level-1 lambda-0.0625 vto--0.7 kp> 58t3 ld-0.18d vidc 3 5 0m vi 5 0 -opticos ncmod nopage .WHJTH OCT-80

20 40 6080100

Figure 2.29 Capacitance and depletion-layer width of an abrupt pn junction as a function of applied voltage and doping concentration on the lightly doped side of the junction11 where NB is the doping density in the epi material and VR is the reverse bias on the junction. The nomograph of Fig. 2.29 can also be used to determine the junction depletion-region width as a function of applied voltage, since this width is inversely proportional to the capacitance. The width in microns is given on the...

23 High Voltage Bipolar Integrated Circuit Fabrication

Integrated-circuit fabrication techniques have changed dramatically since the invention of the basic planar process. This change has been driven by developments in photolithography, processing techniques, and also the trend to reduce power-supply voltages in many systems. Developments in photolithography have reduced the minimum feature size attainable from tens of microns to the submicron level. The precise control allowed by ion implantation has resulted in this technique becoming the...

27000

-1.(91*00 -1.211*00 -1.071.00 -1.S0I-01 -i .511-01 -1.121-01 -2.331-01 -2.571- 02-1.111-01 3.111-01 5.911-01 7.991-01 1.001*00 1.201*00 1.411*00 1.S1I*00 1.111*00 1.971*00-1.991*00 1.991*00 2.001*00 2.001*00 2.001*00 2.001*00 2.001*00 2.001*00 2.001*00 2.001*00-2.001*00 2.001*00 2.001*00 2.001*00 2.001*00 2.001*00 Leff L-lU-XjC 1 9.0* -o.1 0.7Z.IAM (loi ZoofiAib - M -MS. i blooKA fa-MI-M .

3

1.000E+05 1.2562+05 1.5B4E 05 1.9955*05 2.5115*05 3.1625+05 3-981E+05 5.0I1E-05 6.309E+05 7.9432+05 1.0005+06 1.253E+06 1.5812*05 1.9955+06 2.5115.06 3.162E+06 3.9B15-06 5.0115*06 6.309E*06 7 .9435+05 1.0005*07 1.2535+0 i.5845+07 1.9955+07 2.5115*0'' 3.1S25-C7 3.9815*07 5.0115*07 6.3095*0 7 9435*0 I. SBE+08 1.534E*08 1.9955*09 2.5115-09 3.1625+03 3.9915+09 5.0115+08 6.3095+08 7.5435*08 1.0005*09 1.775*02 .775+02 1.765*02 1.755*02 .745*02 1-73E.02 1.71E.02 1.635*02 1.575*02 1.635*02 1.595*02-1....

31

Since Vds3 Vd32, Vm y,32 Vtn, and (W L)3l (W L)32. This equation shows that Icm is dependent on the CM output voltage and independent of the differential output voltage because changes in the drain currents in M31 and M32 due to nonzero V* are equal in magnitude and opposite in sign. Therefore, these changes cancel when the drain currents are summed in (12.62). Applying KVL around the lower transistors A 30-M35 gives Vds3l Vds35 + Vgs33 - (12.63) Assuming that I0 33, we have Vgs30 V .33, and...

35

This last expression shows that the op-amp tail current Icms consists of a constant term 2 i plus a term that depends on Voc-yCM-If 1 31 ld41 h, then KCL requires that Icms 2 i. Using this value in (12.66) gives Voc Vcm, as desired. In practice, mismatches can cause Voc to deviate from Vcm For example, if the drain currents in M3 and M4 are larger than 11, then (12.66) shows that Voc must be larger than VCm to force lcms to be larger than 2 Ix. To see that the CMFB loop here is a negative...

35 30 25 20 15 10 5

Figure 2.63 (a) Plan view and cross section of polysilicon resistor. resistor described in Section 2.6.2 and shown in Fig. 2.42. It displays large tolerance, high voltage coefficient, and high temperature coefficient relative to other types of resistors. Higher sheet resistance can be achieved by the addition of the pinching diffusion just as in the bipolar technology case. MOS Devices as Resistors. The MOS transistor biased in the triode region can be used in many circuits to perform the...

4

Figure 3.5 Unilateral two-port equivalent circuits with (a) Norton output model (b) Thevenin output model. Figure 3.6 Example of loading at the input and output of an amplifier modeled by a two-port equivalent circuit. any two of the three parameters including Gm, Z0, and av specifies the third parameter because Once two of these parameters and the input impedance are known, calculation of the effects of loading at the input and output ports is possible. At low frequencies, the input and output...

4000106 8000106 1200105 1600105 2000105 2400105 2800105 3200105 3600105 4000105 4100105 1800105 5200105 5600105 6000105

-2.921-02-9.411-01 1.871+00 2.701+00 3.351+00 3.781+00 3.971+00 3.901+00 3.591+00 3.051+00 2.301+00-1.121+00 1.541-01 -5.341-01 -1.511+00 -2.401+00 -3.141+00 -3.671+00 -i.981+00 -4.041*00 -3.861+00--3.131+00 -2.7BE+00 -1.971+00 -1.031+00 -2.921-02 fourier compcments of trassiert response v( 10) dc ccmpohdr -4.173d-02 harmooic frequency fourier normalized phase no (hz) compobent component (dbg)

4222

Figure 4.4 shows an MOS version of the simple current mirror. The drain-gate voltage of M is zero therefore, the channel does not exist at the drain, and the transistor operates in the saturation or active region if the threshold is positive. Although the principle of operation for MOS transistors does not involve forward biasing any diodes, M is said to be diode connected in an analogy to the bipolar case. Assume that M2 also operates in the active region and that both transistors have...

4232

Since pF co for an MOS transistor, beta helpers are not used in simple MOS current mirrors to reduce the systematic gain error. However, a beta-helper configuration can increase the bandwidth of MOS and bipolar current mirrors. 4.2.4 Simple Current Mirror with Degeneration 4.2.4.1 Bipolar The performance of the simple bipolar transistor current mirror of Fig. 4.6 can be improved by the addition of emitter degeneration as shown in Fig. 4.7 for a current mirror with two independent outputs. The...

4242

Source degeneration is rarely used in MOS current mirrors because, in effect, MOS transistors are inherently controlled resistors. Thus, matching in MOS current mirrors is improved simply by increasing the gate areas of the transistors.2'3'4 Furthermore, the output resistance can be increased by increasing the channel length. To increase the output resistance while keeping the current and VGS - Vt constant, the W L ratio must be held constant. Therefore, the channel width must be increased as...

4252

The cascode current mirror is widely used in MOS technology, where it does not suffer from finite pF effects. Figure 4.9 shows the simplest form. From (3.107), the small-signal output resistance is Ro ro2 1 + (gm2 + gmblVo l + r0 (4.50) As shown in the previous section, the bipolar cascode current mirror cannot realize an output resistance larger than Pora 2 because Po is finite and nonzero small-signal base current flows in the cascode transistor. In contrast, the MOS cascode is capable of...

5

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5 V

Figure 9.65 Circuit for Problem 9.45. l(jco) 1 How does this frequency compare to the frequency at which av(ja)) 1 (b) Find the phase margin for the cases Qn 0, Cin 4 pF, and Cin 20 pF. 9.43 A technique that allows the return ratio to be simulated using SPICE without disrupting the dc operating point is shown in Fig. 8.60 and explained in Problem B.33. (a) Use that technique to simulate the return ratio for the op amp from Problem 9.21 connected in a noninverting unity-gain configuration for 1...

6

4.0002-06 8.0001-06 1.2001-05 1.6001-05 2.0001-05 2.4001-05 2.8001-05 3.2001-05 3.6001-05 4.0001-05 4.4001-05 4.8001-05 5.2001-05 5.6001-05 6.0001-05 6.1001-05 6.8001-05 7.2001-05 7.6001-05 8.0001-05 8.1001- 05 B 001-05 9.2001-05 9.6001-05 1.0001-04 8.231-05-+---7,531-06 > A 6.611-00 A 1.551-11 A 1.681-11 A 1.771-11 A 1.801-11 A 1.791-11 A 1.731-11 A 1.621-11 A 1 -471-ll-A 1.141-06 A 2.B81-05 > 1.121-04 1.691-04 2.241-04 2.711-01 3.071-04 * 3.291-04 + 3.321-04 3.201-04-+---2.911-04 2.491-04...

6 V

Figure 8.51 Circuit diagram of the 733 wideband monolithic amplifier. 8.20 A commercial wideband monolithic feedback amplifier (the 733) is shown in Fig. 8.51. This consists of a local series-feedback stage feeding a two-stage shunt-shunt feedback amplifier. The current output of the input stage acts as a current drive to the shunt-shunt output stage. (a) Assuming all device areas are equal, calculate the collector bias current in each device. (b) Calculate input impedance, output impedance,...

6210Operational Amplifier Equivalent Circuit

The effect of some of these deviations from ideality on the low-frequency performance of an op amp in a particular application can be calculated using the equivalent circuit shown in Fig. 6.14. (This model does not include the effects of finite PSRR or CMRR.) Here, the two current sources labeled bias represent the average value of dc current flowing into the input terminals. The polarity of these current sources shown in Fig. 6.14 applies for an npn transistor input stage. The current source...

622 Input Offset Current

For the emitter-coupled pair shown in Fig. 6.11, the two input bias currents will be equal only if the two transistors have equal betas. Geometrically identical devices on the same IC die typically display beta mismatches that are described by a normal distribution with a standard deviation of a few percent of the mean value. Since this mismatch in the two currents varies randomly from circuit to circuit, it cannot be compensated by a fixed resistor. This aspect of op-amp performance is...

627Input Resistance

In bipolar transistor input stages, the input resistance is typically in the 100 kfl to 1 Mil range. Usually, however, the voltage gain is large enough that this input resistance has little effect on circuit performance in closed-loop feedback configurations. Op amps whose inputs are connected to the gates of MOS transistors have csscnUally infinite input resistance in principle. In practice, however, MOS-transistor gates connected through package pins to the outside world must be protected...

628Output Resistance

General-purpose bipolar op amps usually use a buffer as an output stage, which typically produces an output resistance on theofder of 40 fi to 100 0. On the other hand, in MOS technologies, internal op amps usually do not have to drive resistive loads. therefore*.' internal MOS op amps usually do not use a buffer output stage, and the resulting output resistance can be much larger than in the bipolar case. In both cases, however, the output resistance does not strongly affect the closed-loop...

629Frequency Response

Because of the capacitances associated with devices in the op amp, the voltage gain decreases at high frequencies. This fall-off must usually be controlled by the addition of extra capacitance, called compensation capacitance, to ensure that the circuit does not oscillate when connected in a feedback loop. (See Chapter 9.) This aspect of op-amp behavior is characterized by the unity-gain bandwidth, which is the frequency at which the magnitude of the open-loop voltage gain is equal to unity....

63 Basic Two Stage MOS Operational Amplifiers

Figure 6.15 shows a schematic of a basic two-stage CMOS op amp.4 5-6 A differential input ctdfTA nrttroc o f . 11------1 l______i ----o -- jti uiuwviiLiai input stage drives an active load followed by a second gain stage. An output stage is usually not - -------j wwv,. & clin -vu uutjjui suige is usuauy not used but may be added for driving heavy loads off-chip. This circuit configuration provides good common-mode range, output swing, voltage gain, and CMRR in a simple circuit that Figure...

632Output Swing

The output swing is defined to be the range of output voltages V0 Vo + va for which all transistors operate in the active region so that the gain calculated in (6T.56) is approximately constant. From inspection of Fig. 6.16, M operates in the triode region if the output voltage is less than VOV6 V s- Similarly, My operates in the triode region if the output voltage is more than Vod Vovi I Therefore, the output swing is Vov6 - Vss < VDD - Vov7 (6.61) This inequality shows that the op amp can...

635 Common Mode Input Range

The common-mode input range is the range of dc common-mode input voltages for which all transistors in the first stage of the op amp operate in the active region. To operate in the active region, the gate-drain voltages of -channel transistors must be less than their thresholds so that their channels do not exist at their drains. Similarly, p-channel transistors operate in the active region only if their gate-drain voltages are more than their thresholds, again so that their channels do not...

638Layout Considerations

A basic objective in op-amp design is to minimize the mismatch between the two signal paths in the input differential pair so that common-mode input signals are rejected to the greatest possible extent. Mismatch affects the performance of the differential pair not only at dc, where it causes nonzero offset voltage, but also at high frequencies where it reduces the common-mode and power-supply rejection ratios. Figure 6.22a shows a possible layout of a differential pair. Five nodes are labeled...

66 MOS Folded Cascode Operational Amplifiers

Figure 6.26 shows two cascode circuits where VDD 0 for simplicity. In Fig. 6.26a, both Mi and Mm are p-channe devices. In Fig. 6.26b, M is still a p-channel device but M A Figure 6.26 shows two cascode circuits where VDD 0 for simplicity. In Fig. 6.26a, both Mi and Mm are p-channe devices. In Fig. 6.26b, M is still a p-channel device but M A Figure 6.26 (a) Standard cascode configuration. (b) Folded-cascode configuration. is now an -channel device. In both cases, however, M is connected in a...

67 MOS Active Cascode Operational Amplifiers

One way to increase the gain of the folded-cascode op amp without cascading additional stages is to add another layer of cascodes. See Problem 6.21. Although this approach gives a gain on the order of (gmr0)3, it reduces the output swing by at least another overdrive in each direction. This reduction becomes increasingly important as the difference between the power-supply voltages is reduced in scaled technologies. To increase the op-amp gain without reducing the output swing, the...

692 Design of Low InputCurrent Operational Amplifiers

In instrumentation applications in which the signal source has a low internal impedance, the input offset voltage and its associated drift usually place a lower limit on the dc voltage than can be resolved. When the source impedance is high, however, the input bias current and input offset current of the op amp flowing in the source resistance or the gain-setting resistors can be important in limiting the ability of the circuit to resolve small dc signals. Furthermore, many applications involve...

70000e01 60000101 50000e01 40000101 30000e01 20000b01 10000e01

1.0000E-01 2.00001-01 3.0000E-01 4.0000E-01 5.0000B-01 6.0000E-01 7.0000E-01 .00001-01 9.0000E-01 1.0000E+00 1.1000E+00 1.20001+00 1.3000E+00 1.4000E+00 1.5000E+00 1. OOOE+OO 1.7000E+00 1.8000E+00 1.9000E+00 2.0000E+00 2.1000E+00 2.2000E+00 2.3000E+00 2.4000E+00 2.5000E+00 VOLTAGE 17 200 1.327E+00 1.1818+00 9.983E-01 9.2748-01 9.247E-01 9.221E-01 9.196E-01 9.1718-01 9.1451-01 9.120E-01 9.095E-01 9.070E-01 9.0441-01 9.019E-01 8.9941-01 8.969E-01 I.944E-01 8.919E-01 8.894E-01 8.869E-01 8.844E-01...

72 Single Stage Amplifiers

The basic topology of the small-signal equivalent circuits of bipolar and MOS single-stage amplifiers are similar. Therefore in the following sections, the frequency-response analysis for each type of single-stage circuit is initially carried out using a general small-signal model that applies to both types of transistors, and the general results are then applied to each type of transistor. The general small-signal transistor model is shown in Fig. 7.1. Table 7.1 lists the parameters of this...

783

Common centroid geometry, 440-442, 476,477 configuration, 202 Common-collector-common-emitter configuration, 202 Common-collector configuration, 191, 503 Common-drain configuration, 195, 509, 591 Common-emitter-common-base configuration, see Cascode configuration Common-emitter configuration, 175, 490, 494 Common-emitter frequency response, 490, 494 Common-emitter output stage, 576 Common-gate configuration, 186, 188, 190.515, 525 Common-gate frequency response, 515 Common-mode feedback, 228,...

8 9

Figure 9.49 Response of the circuit of Fig. 9.48 when a 5-V step input is applied, (a) Response predicted by (9.125) for the 741 op amp. (b) Measured response for the 741. The current from the input stage, which charges the compensation capacitor, is lx. The large-signal transfer characteristic from the op-amp differential input voltage Vid to Ix is that of a differential pair, which is shown in Fig. 9.51. From Fig. 9.51, the maximum current available to charge C is 211, which is the tail...

81 Ideal Feedback Equation

Consider the idealized feedback configuration of Fig. 8.1. In this figure 5, and SQ are input and output signals that may be voltages or currents. The feedback network (which is usually linear and passive) has a transfer function and feeds back a signal Sfb to the input. At the input, signal Sfb is subtracted from input signal at the input differencing node. Error signal Se is the difference between St and Sfb, and S is fed to the basic amplifier with transfer function a. Note that another...

810e01

A j*- 7.5724E+02 A CM- 2.6762E-01 A_CM2EM- 1.4495E-02 A_CM2CM- -3.4873E+02 A_DM A_CM- 2.8295E+03 A_EM A_CM2DM- 5.2242E+04 AJ* AJ*2CM- -2.17141*00 -2.+WS+o.i5< V0, < 2.-0' 15- o.iS - -7V< Voi< L7V (a.) VOM - Voc - VcBiAs - to 5-0.S- -l-Vovfc Vc c - V -- Ipi Vovsl zjigj IValI h i ) - 2. out r swing. C fll peaje -to peak.)aw be achieved. - (20 Id) - 7 Gl) - ss+Vo v7 < Vo I < dd- l Vov I - 10O f2o.53jdoo Zo iMl* IOO Os . l T' wJ*

815

A computer simulation of this circuit using SPICE gave a -3-dB frequency of 205 kHz, which is close to the calculated value. The simulation gave three negative real poles with magnitudes 205 kHz, 4.02 MHz, and 39.98 MHz. There were two positive real zeros with magnitudes 477 MHz and 955 MHz. From the simulation, the sum of the reciprocals of the pole magnitudes was 815 ns, which exactly equals the sum of the zero-value time constants as calculated by hand. An exact analysis of Fig. 7.28 would...

82 Gain Sensitivity

In most practical situations, gain a of the basic amplifier is not well defined. It is dependent on temperature, active-device operating conditions, and transistor parameters. As mentioned previously, the negative-feedback loop reduces variations in overall amplifier gain due to variations in a. This effect may be examined by differentiating (8.5) to obtain If a changes by da, then A changes by 5 A where

843 Shunt Series Feedback

The shunt-series configuration is shown in Fig. 8.11. The feedback network samples ia and feeds back a proportional current ifb fiD. Since the desired output signal is a current i0, it is more convenient to represent the output of the basic amplifier with a Norton equivalent. In this case both a and are dimensionless current ratios, and the ideal input source is a 8,5 Practical Configurations and the Effect of Loading 563 Basic amplifier 8,5 Practical Configurations and the Effect of Loading...

854 Shunt Series Feedback

Shunt-series feedback is shown schematically in Fig. 8.11. In this case the basic amplifier and the feedback network have common input voltages and output currents, and hybrid g parameters as defined in Fig. 8.29 are best suited for use in this case. The feedback circuit is shown in Fig. 8.30a, and, at the input, we find that (ys + glla + gllf)Vi + (gl 2 + g 12 f)io node, and the feedback function can be identified as The gain a of the basic amplifier is determined by calculating the current...

882 Closed Loop Impedance Formula Using Return Ratio

Feedback affects the input and output impedance of a circuit. In this section, a useful expression for the impedance at any port in a feedback circuit in terms of return ratio9 is derived. Consider the feedback circuit shown in Fig. 8.44. This feedback amplifier consists of linear elements passive components, controlled sources, and transistor small-signal models. A controlled source k that is part of the small-signal model of an active device is shown explicitly. The derivation is carried out...

883 Summary ReturnRatio Analysis

Return-ratio analysis is an alternative approach to feedback circuit analysis that does not use two-ports. The loop transmission is measured by the return ratio Sft. The return ratio is a different measure of loop transmission than af from two-port analysis. (The return ratio is referred to as loop gain in some textbooks. That name is not associated with 91 here to avoid confusion with T af, which is called loop gain in this chapter.) For negative feedback circuits, 2ft > 0. In an ideal...

91

The return ratio can be used to check stability of an amplifier with a single feedback loop because A f_ and d are stable transfer functions associated with passive networks, and Ms) is stable because it is the signal transfer around a loop that consists of one gain stage or a cascade of stable gain stages. Therefore the zeros of 1 + 2ft(s), which are poles of the closed-loop gain A, determine the stability of the feedback circuit.24 From the Nyquist stability criterion, these zeros are in the...

943 Two Stage MOS Amplifier Compensation

The basic two-stage CMOS op amp topology shown in Fig. 6.16 is essentially identical to its bipolar counterpart. As a consequence, the equivalent circuit of Fig. 9.21 can be used to represent the second stage with its compensation capacitance. The poles of the circuit are again given by (9.32) and (9.33) and the zero by (9.27a). In the case of the MOS transistor, however, the value of gm is typically an order of magnitude lower than for a bipolar transistor, and the break frequency caused by...

944 Compensation of Single Stage CMOS Op Amps

Single-stage op amps, such as the telescopic cascode or folded cascode, have only one gain stage therefore Miller compensation is not possible. These op amps have high open-loop output resistance and are typically used in switched-capacitor circuits, where the load is purely capacitive. Therefore, the dominant pole is associated with the output node, and the load capacitor provides the compensation. A simplified, fully differential, telescopic-cascode op amp is shown in Fig. 9.30 . The...

945 Nested Miller Compensation

Many feedback circuits require an op amp with a high voltage gain. While cascoding is commonly used to increase the gain in op amps with a total supply voltage of 5 V or more, cascoding becomes increasingly difficult as the power-supply voltage is reduced. (See Chapter 4.) To overcome this problem, simple gain stages without cascoding can be cascaded to achieve high gain. When three or more voltage-gain stages must be cascaded to achieve the desired gain, the op amp will have three or more...

95 Root Locus Techniques118

To this point the considerations of this chapter have been mainly concerned with calculations of feedback amplifier stability and compensation using frequency-domain techniques. Such techniques are widely used because they allow the design of feedback amplifier compensation without requiring excessive design effort. The root-locus technique involves calculation of the actual poles and zeros of the amplifier and of their movement in the s plane as the low-frequency, loop-gain magnitude T0 is...

951 Root Locus for a Three Pole Transfer Function

Consider an amplifier whose transfer function has three identical poles. The transfer function can be written as where aQ is the low-frequency gain and p is the pole magnitude. Consider this amplifier placed in a negative-feedback loop as in Fig. 9.1, where the feedback network has a transfer function , which is a constant. If we assume that the effects of feedback loading are small, the overall gain with feedback is hi gmoRog,nlRigm2R2 20,000 86 dB Figure 9.35 Root locus for a feedback...

952

9 K II > 2 > fct (1+ (O.952)(2)) - 158 XSL mos oimnmiUi pair with socrce-isghierated correot-mirror load m 2 3 4 4 mos tt 50u l-1u 2 6 0 4 4 mds w*50u l 1u bot that cobbctibg the bodt to the soorce elduhatcs for n-chan, kp un*cox 550*1.38b-7 - 127 a v 2 for p-chan, kp dp cox 250*1.38e-7 - 58 da v* 2 .mockl mos mos izvel-1 lakbda-0.105263 vto-o.7 kp-1270 ld-0.12u .modkl fmos fmos level 1 lambda-0.0625 vto--0.7 kp 58u ld-0.18u ywc 3 5 0* vi 5 0 .options bonod bopage dc vi -0.01 0.01 0.002...

953 Root Locus for Dominant Pole Compensation

Consider an op amp that has been compensated by creation of a dominant pole at Pl. If we assume the second most dominant pole is at p2 and neglect the effect of higher order poles, the root locus when resistive feedback is applied is as shown in Fig. 9.40. Using rules 1 and 2 indicates that the root locus exists on the axis between Pl and p2, and the breakaway point is readily shown to be using rule 6. Using rules 7 and 8 shows that the asymptotes are at 90 to the real axis and meet the axis at...

954 Root Locus for Feedback Zero Compensation

The techniques of compensation described earlier in this chapter involved modification of the basic amplifier only. This is the universal method used with op amps that must be compensated for use with a wide variety of feedback networks chosen by the user. However, this method is quite wasteful of bandwidth, as was apparent in the calculations. In this section, a different method of compensation will be described that involves modification of the feedback path and is generally limited to...

96 Slew Rate

The previous sections of this chapter have been concerned with the small-signal behavior of feedback amplifiers at high frequencies. However, the behavior of feedback circuits with large input signals (either step inputs or sinusoidal signals) is also of interest, and the effect of frequency compensation on the large-signal, high-frequency performance of feedback amplifiers is now considered. t Figure 9.48 Circuit for testing slew-rate performance. and f0 is the -3-dB frequency. Since the...

962 Methods of Improving Slew Rate in Two Stage Op Amps

In order to examine methods of slew-rate improvement, a more general analysis is required. This can be performed using the circuit of Fig. 9.52, which is a general representation of an op amp circuit. The input stage has a small-signal transconductance gmI and, with a large input voltage, can deliver a maximum current Ixm to the next stage. The compensation is shown as the Miller effect using the capacitor C, since this representation describes most two-stage integrated-circuit op amps. From...

965 Effect of Slew Rate Limitations on Large Signal Sinusoidal Performance

The slew-rate limitations described above can also affect the performance of the circuit when handling large sinusoidal signals at higher frequencies. Consider the circuit of Fig. 9.48 with a large sinusoidal signal applied as shown in Fig. 9.57a. Since the circuit is connected as a voltage follower, the output voltage V0 will be forced to follow the V, waveform. The maximum value of dVJdt occurs as the waveform crosses the axis, and if V, is given by As long as the value of dVi dt max given by...

A

Is the offset voltage contribution from the transistors themselves, as reflected in the mismatch in saturation current. Mismatch factors ARc Rc and AIs Is are actually random parameters that take on a different value for each circuit fabricated, and the distribution of the observed values is described by a probability distribution. For large samples the distribution tends toward a normal, or Gaussian, distribution with zero mean. Typically observed standard deviations for the preceding mismatch...

Ttt Tt7

The block diagram from return-ratio analysis in Fig. 8.42 is the same as Fig. 9.1 if a is replaced by b, f is replaced by 1 A , and the direct feedforward d is negligible. (The contribution of feedforward through the feedback network to a is also neglected in the analysis in Sections 9.2-9.5, since feedforward introduces one or more zeros into a(s), but only one- and two-pole a(s) are considered in these sections. Neglecting the feedforward in a or the direct feedthrough d is reasonable if its...

Vod I Voc VcMWod

4 4 V23 - (Vod 2)2 ) 8 4V2v23 - (Vod 2)2 If Vod 21 < 2Vov23 , this equation reduces to (12.56). To interpret (12.61), first consider the case when Voc VCM. Then (12.61) shows that the CM-sense output current is constant with Icms 20. Whereas Icms is constant, (12.59) and (12.60) show that Id22 and Im are not constant if Vod is nonzero and time-varying, and Id22 and Id23 are nonlinear functions of Vod (see the plot in Fig. 3.51). However, the variation in Id22 due to nonzero V0d is equal and...

A412

Matched current sources are often required in MOS analog integrated circuits. The factors affecting this mismatch can be calculated using the circuit of Fig. 4.52. The two transistors Mi and M2 will have mismatches in their W L ratios and threshold voltages. The drain Figure 4.53 Current mirror with two outputs used to compare voltage- and current-routing techniques. circuit with desirable properties. For example, a self-biased band-gap reference might be used to make fa insensitive to changes...

A42 Input Offset Voltage Of Differential Pair With Active Load A421 Bipolar

For the resistively loaded emitter-coupled pair, we showed in Chapter 3 that the input offset voltage arises primarily from mismatches in Is in the input transistors and from mismatches in the collector load resistors. In the active-load case, the input offset voltage results from nonzero base current of the load devices and mismatches in the input transistors and load devices. Refer to Fig. 4.25a. Assume the inputs are grounded. If the matching is perfect and if pF > in T3 and T4, Equation...

A422 Mos 334

5.2 The Emitter Follower As an Output Stage 344 5.2.1 Transfer Characteristics of the Emitter-Follower 344 5.2.2 Power Output and Efficiency 347 5.2.3 Emitter-Follower Drive Requirements 354 5.2.4 Small-Signal Properties of the Emitter Follower 355 5.3 The Source Follower As an Output Stage 356 5.3.1 Transfer Characteristics of the Source Follower 356 5.3.2 Distortion in the Source Follower 358 5.4 Class B Push-Pull Output Stage 362 5.4.1 Transfer Characteristic of the Class B Stage 363 5.4.2...

A92 Roots Of A Quadratic Equation

A second-order polynomial often appears in the denominator or numerator of a transfer function, and the zeros of this polynomial are the poles or zeros of the transfer function. In this appendix, the relationships between the zeros of a quadratic and its coefficients are explored for a few specific cases of interest. Also, the conditions under which a dominant root exists are derived. Consider the roots of the quadratic equation A9.2 ROOTS OF A QUADRATIC EQUATION 693 The two roots of this...

Ac Analtsis

1.0008+01 1.5811+01 .5118+01 3.9811+01 i.3098*01 1.0002+02 1.5818+02 2.5111+02 3.9818+02 6.309B+02 1.0008+03 1.5818*03 2.5118+03 3.9818*03 6.309E+03 1.0008*01 1.5818+01 2.5118+01 3.9818+01 (.3098+01 1.0008+05 1.5818+05 2.5118+05 3.9818*05 8.3091+05 l.OOOE+OS 1.5818+06 2.5118+06 3.9818+06 8.3098+06 1.0008+07 1.5818+07 2.5118+07 3.9818+07 S.3098+07 l.OOOB+OB

Acquisitions Editor

EDITORIAL ASSISTANT Susannah Barr SENIOR MARKETING MANAGER Katherine Hepburn PRODUCTION SERVICES MANAGER Jeanine Furino PRODUCTION EDITOR Sandra Russell PRODUCTION MANAGEMENT SERVICES Publication Services, Inc. Cover courtesy of Dr. Kenneth C. Dyer and Melgar Photography. This book was set in 10 12 Times Roman by Publication Services, Inc. and printed and bound by Hamilton Printing Company. The cover was printed by Lehigh Press, Inc. This book was printed on acid-free paper. Copyright 2001 John...

B 3 a3

And the coefficients in the numerator are 0 g m< ) g m g mlR()R gmfO gmOgmf R() n gmo(gml gmf )RoRXCmX + (gm0 gmfo)RoCm2 - gmfoR (CX + Cm 1) - gmfoRoCu gmQgmf RoRXC n2 (gmO - gmfo)RoRl(Cx + CmX)Cm2 - gmfQRQRx Ci + CmX)Co The coefficients of .v and s2 in the numerator include both positive and negative terms. Therefore, they can be set to zero, which eliminates the zeros, by properly choosing gmf0 and gmf . As in (9.73) above, these values depend on parasitic capacitances C0 and Cx, which are...

Bias

Figure 6.27 Simplified schematic of a folded-cascode op amp. to several thousand. Because of the action of the current mirror M3 - M4, variation in the drain current of Mi and M2 contribute constructively to the transconductance. Therefore, To find R0, both inputs are connected to ac ground. Although the input voltages do not move in this case, the sources of Mi - M2 do not operate at ac ground. However, connecting this node to small-signal ground as shown in Fig. 6.29a causes little change in...

Bias3

Assume VDD V.v.s' 1.65 V and that the matching is perfect. When the dc input voltage Vj 0, assume that all transistors except MIOf, and Mn4 operate in the active region with equal overdrive magnitudes. To make the gain insensitive to small shifts in the operating point, design the circuit so that the magnitude of the drain-source voltage for each transistor operating in the active region exceeds the magnitude of its overdrive by at least 100 mV. Ignore the body...

Bztaac Ft

0 Q1 0 NPB 2.8(11-04 (. 181-03 (.2541-01 1.07(1-01 5.1781-01 5.1781-01 8.9121-04 2.3131+01 2.2141-01 4.3771+02 5.0001+01 1.4311+02 0. 0. 0. 0. 0 Q2 0 NPH 2.8(11-04 ( (181-03 (.2541-01 1.07(1-01 5.1781-01 5.1781-01 8.9121-04 2.3131+01 2.2141-01 4.3771+02 5.0001+01 1.4311+02 0. 0. 0. 0. 0 Q3 0 HPN 3.1(51-05 3.1(51-03 5.8801-01 2.5911+00 -2.0031+00 -1.4851+00 8.2221-03 1.0001+02 1.02(1-01 9.7491+02 5.0001+01 1.1311+11 0. 0. 0. 0. 0 Q4 0 HPM 3.1(51-05 3.1651-03 5.8801-01 2.5911+00 -2.0031+00...

Mfb

Figure 4.38 (a) Self-biasing Vbe reference, (b) Self-biasing V, reference. the start-up circuit must not interfere with the normal operation of the reference once the desired operating point is reached. The Vg -referenced current source with a typical start-up circuit used in bipolar technologies is illustrated in Fig. 4.39a. We first assume that the circuit is in the undesired zero-current state. If this were true, the base-emitter voltage of Ti would be zero. The base-emitter voltage T2 would...

Okk

Equation 9.127 predicts a constant rate of change of VQ during the slewing period, which is in agreement with the experimental observation. For the 741 op amp, h 12 (jiA and C 30 pF giving dVa dt 0.8 V xs, which is close to the measured value. The above calculation of slew rate was performed on the circuits of Fig. 9.50, which have no overall feedback. Since the input stage produces a constant output current that is independent of its input during the slewing period, the presence of a feedback...

Cascodb Current Mirror With Level Shift

VDD 100 0 3 TO 2 0 0.2 IR 100 4 SI. 84U BOTE THAT IR > 50 UA BECAUSE THIS CURRHH MIRROR HAS A NONZERO STSTEKATIC GAIN ERROR. IK 51.9 UA IS CHOSEN ET TRIAL AND ERROR TO FORCE THE OUTPUT CURRENT TO BE 50 UA, AS GIVEN IN THE PROBLEM. IN THE HAND CALCULATION, THE REQUIRED WIDTH WAS CALCULATED TO BE 16.5 MICRONS HOWEVER, TRIAL AND ERROR IN SPICE SHOWS THAT THE WIDTH BAS TO BE INCREASED TO 18 MICRONS TO OPERATC Ml AND M2 BARELY IN THE ACTIVE REGION. THIS DIFFERHKE STDB FRO THE OBSERVATION THAT ALL...

Chapter

10.2 Precision Rectification 702 10.3 Analog Multipliers Employing the 10.3.1 The Emitter-Coupled Pair as a Simple Multiplier 708 10.3.2 The dc Analysis of the Gilbert Multiplier Cell 710 10.3.3 The Gilbert Cell as an Analog Multiplier 712 10.3.4 A Complete Analog Multiplier 715 10.3.5 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Dectector 716 10.4 Phase-Locked Loops (PLL) 720 10.4.1 Phase-Locked Loop Concepts 720 10.4.2 The Phase-Locked Loop in the Locked Condition 722 10.4.3...

Cmo

9.999E 03 1.2581*04 1.5B1E-0I 1.9951+01 1-511E+D4 3 1621+01 1.9111*01 5.0111*01 6.3091*01 .9(31+01 1.0001*05 . 58E O5 1.5 IE*05 1.995E+05 2.511E-05 3. E-35 5.9111*05 5.011E* 05 S.309E.05 .943E* 5 1.000E-06 l. SK*06 1.584E+06 1.9951*06 2.5111*06 3 152S.06 3.9811*06 5.011S*06 6.3091*36 7 9432*36 1 3001*07 1.258E.CT 1.5811*07 1 995S.O 2.5111*0 3 162E*07 3.9811*07 5 0 1E.07 6.339E+07 7 9131*0* 1 0001*08 8.2811-05 2.0001+02 4.8041-04 4.163e+05 0. 5.795e-13 2.0001+02 7.747e+06 ac ahalysis 3.831*01-'...

Cmos Amp Vdd 1 0 15v Vss 2 0 15v

Ml 7 5 4 4 P H 1500 L 0.720 M2 I 6 4 4 P **1500 L 0.720 M3 7 7 2 2 M **500 L 0.72D M4 I 7 2 2 M -500 L 0.720 M5 4 3 1 1 P W-150U L 0.72U *7 9 3 1 1 P 1500 L 0.720 Ml 3 3 1 1 P * 1500 La0.720 WHiil H*100V L*0.720 IBIAS 3 2 2000A M9 10 1 I 2 S 1.20 U0.l20 CCCHP 10 9 5PF .NOSEL a MBS LEVEL 1 XP 1940 VTO-O.6 LAMBDMO.027778 . DEL P PWS LEVEL l XP-64.70 VTO 0.8 LAMBDA 0.055556 BBS LAMBDA* (DXD DVDS) LEFF*0.020 0.720*0.027778 PMOS LAMBDA* (DXD DVDS) LEFF*0.040 0.720*0.055556