004

Figure 2.60 Typical experimental variation of drain current as a function of the square root of gate-source voltage in the active region. Table 2.4 Summary of Process Parameters for a Typical Silicon-Gate w-Well CMOS Process with 0.4 jum Minimum Allowed Gate Length Table 2.4 Summary of Process Parameters for a Typical Silicon-Gate w-Well CMOS Process with 0.4 jum Minimum Allowed Gate Length

0045

These circuits are not fully supply independent because the base-emitter or gate-source voltages of T change slightly with power-supply voltage. This change occurs because the collector or drain current of T is approximately proportional to the supply voltage. The resulting supply sensitivity is often a problem in bias circuits whose input current is derived from a resistor connected to the supply terminal, since this configuration causes the currents in some portion of the circuit to change...

02

Figure 4.59 Cascode active-load circuit for Problem 4.16. Figure 4.59 Cascode active-load circuit for Problem 4.16. drwn 1 ixm and Xd 0. Use Table 2.3 for other parameters. 4.15 Repeat Problem 4.14, but now assuming that 2 kil resistors are inserted in series with the sources of M3 and M4. Ignore the body effect. 4.16 Determine the unloaded voltage gain v0 v, and output resistance for the circuit of Fig. 4.59. Neglect Verify with SPICE and also use SPICE to plot the large-signal Vq-Vi transfer...

03

Figure 5.18 Simplified schematic of the output stage of the 709 op amp. The limiting values that Va can take are determined by the driver stage. When V, is taken large positive, V decreases until saturates, at which point the negative voltage limit V is reached y o -VCC + VC 3(sat) Vbe2 (5.76) For values of Vx between ( VCc + C 3 sat)) and (- VBE(on)), both Q3 and Q2 are in the forward-active region, and V0 follows V with Q2 acting as an emitter follower. As Vi is taken negative, the current in...

035

This equation shows that the pulse rise time is directly related to the 3-dB frequency of the circuit. For example, if _3dB 10 MHz, then (7.160) predicts tr 35 ns. If a square wave is applied to a circuit with a single-pole transfer function, the response is as shown in Fig. 7.39 b. The edges of the square wave are rounded as described above for a single pulse.

04

Figure 1.43 Drain current versus drain-source voltage in weak inversion. The transconductance of an MOS transistor operating in weak inversion is identical to that of a corresponding bipolar transistor, as shown in (1.182), except for the factor of 1 In Cox (CjS + Cnx). This factor stems from a voltage divider between the oxide and depletion capacitors in the MOS transistor, which models the indirect control of the gate on the surface potential. From (1.253), the ratio of the transconductance...

05

Figure 2.35 Typical parameters for lateral pnp transistors with 900 (Jim2 emitter area in a highvoltage, thick-epi process. Figure 2.35 Typical parameters for lateral pnp transistors with 900 (Jim2 emitter area in a highvoltage, thick-epi process. high-voltage, thick-epi process is shown in Fig. 2.36a. Thep-type emitter diffusion for this particular substrate pnp geometry is rectangular with a rectangular hole in the middle. In this hole an n+ region is formed with the npn emitter diffusion to...

09

Compare your answer with a SPICE simulation. Also, compare your answer to the result that would apply without mismatch. 4.19 Although Gm cni of a differential pair with a current-mirror load can be calculated exactly from a small-signal diagram where mismatch is allowed, the calculation is complicated because the mismatch terms interact, and the results are difficult to interpret. In practice, the mismatch terms are often a small fraction of the corresponding average values, and the...

1

The validity of (1.51) depends on W2Bl2TbDn 1 and (Dp Dn)(WB Lp)(NA ND) < sc 1, and this is always true if 3F is large see (1.48) . The term y in (1.51) is called the emitter injection efficiency and is equal to the ratio of the electron current (npn transistor) injected into the base from the emitter to the total hole and electron current crossing the base-emitter junction. Ideally y 1, and this is achieved by making ND NA large and WB small. In that case very little reverse injection occurs...

1 1

Equation 3.84 shows that the body effect reduces the output resistance, which is desirable because the source follower produces a voltage output. This beneficial effect stems from the nonzero small-signal current conducted by the gmb generator in Fig. 3.25b, which increases the output current for a given change in the output voltage. As ra oo and Rl oo, this output resistance approaches l (gm + gmb). The common-gate input resistance given in (3.54) approaches the same limiting value. As with...

1 1 1

Figure 9.45 Poles of the transfer function of the feedback amplifier of Fig. 9.41. The transfer function contains no zeros. near the jco axis, which would give rise to an excessively peaked response. In practice, oscillation can occur because higher magnitude poles do exist and these would tend to give a locus of the kind of Fig. 9.39, where the remote poles cause the locus to bend and enter the right half-plane. (Note that this behavior is consistent with the alternative approach of...

10

Allowed dimensions of passive devices have also decreased.) This trend is driven primarily by economics in that reducing dimensions increases the number of devices and circuits that can be processed at one time on a given wafer. A second benefit has been that the frequency capability of the active devices continues to increase, as intrinsic fj values increase with smaller dimensions while parasitic capacitances decrease. Vertical dimensions such as the base width of a bipolar transistor in...

10 V

Figure 11.54 Differential-pair input stage for Problem 11.14. figure of this circuit in decibels for 10 kft using the following data. Neglect flicker noise and capacitive effects. (b) If the device has fT 500 MHz, calculate the frequency where the noise figure is 3 dB above its low-frequency value. 11.20 (a) Neglecting capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.52 with Rs 5 kft. Use data as in Problem 11.10. (b) If the flicker noise corner frequency for...

100

V2 v0- Vbe20 (10 - 0.525) V 9.475 V Vi v2 - Vbe23 (9.475 - 0.613) V 8.862 V 5.4.4 All-npn Class B Output Stage7-6-9 The Class B circuits described above are adequate for many integrated-circuit applications where the output power to be delivered to the load is of the order of several hundred milliwatts or less. However, if output-power levels of several watts or more are required, these circuits are inadequate because the substrate pnp transistors used in the output stage have a limited...

1000

V0(t) 0.031 sin (27t x 102r) - 51 Operating the loop with no loop filter has several practical drawbacks. Since the phase detector is really a multiplier, it produces a sum frequency component at its output as well as the difference frequency component. This component at twice the carrier frequency will be fed directly to the output if there is no loop filter. Also, all the out-of-band interfering signals present at the input will appear, shifted in frequency, at the output. Thus, a loop filter...

101

3.3.7 Common-Drain Configuration (Source Follower) The common-drain configuration is shown in Fig. 3.25a. The input signal is applied to the gate and the output is taken from the source. From a large-signal standpoint, the output voltage is equal to the input voltage minus the gate-source voltage. The gate-source voltage consists of two parts the threshold and the overdrive. If both parts are constant, the resulting output voltage is simply offset from the input, and the small-signal gain would...

102 Precision Rectification

Perhaps the most basic nonlinear operation performed on time-varying signals is rectification. An ideal half-wave rectifier is a circuit that passes signal currents or voltages of only one polarity while blocking signal voltages or currents of the other polarity. The transfer characteristic of an ideal half-wave rectifier is shown in Fig. 10.1. Also shown in Fig. 10.1 is the transfer characteristic of a second useful rectifier, the full-wave type. Practical rectifiers can be divided into two...

1034 A Complete Analog Multiplier3

In order to be useful in a wide variety of applications, the multiplier circuit must develop an output voltage that is referenced to ground and can take on both positive and negative values. The transistors Q3, Q4, Q5, Q6, Q7t and 8, shown in Fig. 10.13, are referred to as the multiplier core and produce a differential current output that then must be amplified, converted to a single-ended signal, and referenced to ground. An output amplifier is thus required, and the complete multiplier...

1035 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector

The four-quadrant multiplier just described is an example of an application of the multiplier cell in which all the devices remain in the active region during normal operation. Used in this way the circuit is capable of performing precise multiplication of one continuously varying analog signal by another. In communications systems, however, the need frequently arises for the multiplication of a continuously varying signal by a square wave. This is easily accomplished with the multiplier...

104 Phase Locked Loops PLL

The phase-locked loop concept was first developed in the 1930s.4 It has since been used in communications systems of many types, particularly in satellite communications systems. Until recently, however, phase-locked systems have been too complex and costly for use in most consumer and industrial systems, where performance requirements are more modest and other approaches are more economical. The PLL is particularly amenable to monolithic construction, however, and integrated-circuit...

1041 Phase Locked Loop Concepts

A block diagram of the basic phase-locked loop system is shown in Fig. 10.18. The elements of the system are a phase comparator, a loop filter, an amplifier, and a voltage-controlled oscillator. The voltage-controlled oscillator, or VCO, is simply an oscillator whose frequency is proportional to an externally applied voltage. When the loop is locked on an incoming periodic signal, the VCO frequency is exactly equal to that of the incoming signal. The phase detector produces a dc or...

1042 The Phase Locked Loop in the Locked Condition

Under locked conditions, a linear relationship exists between the output voltage of the phase detector and the phase difference between the VCO and the incoming signal. This fact allows the loop to be analyzed using standard linear feedback concepts when in the locked condition. A block diagram representation of the system in this mode is shown in Fig. 10.20. The gain of the phase comparator is KD V rad of phase difference, the loopfilter transfer function is F(s), and any gain in the forward...

11

Note that both (1.21) and (1.22) predict values of Cj approaching infinity as Vd approaches i o- However, the current flow in the diode is then appreciable and the equations no longer valid. A more exact analysis2 3 of the behavior of Cj as a function of Vd gives the result shown in Fig. 1.3. For forward bias voltages up to about i y0 2, the values of C predicted by (1.21) are very close to the more accurate value. As an approximation, some computer programs approximate Cj for VD > < 0 2 by...

111

Figure 10.15 Input and output spectra for a balanced modulator. This dc component can be introduced intentionally to provide conventional amplitude modulation or it can be the result of offset voltages in the devices within the modulator, which results in undesired carrier feedthrough in suppressed-carrier modulators. Note that the balanced modulator actually performs a frequency translation. Information contained in the modulating signal Vm(t) was originally concentrated at the modulating...

1115

Check headroom requirements in the bias circuit For the. branch induct ing M,3 0, this branch operate with all transistors in the active region if Voy C 0-33 V For the branch including M 0.1 v) - VT in 4- 0.7 v- (-ifc). 0 U,. in 4 36 mV (neglect) - -0.8 V 5 -0. -0 -0 -0.7-(-l'5) 3 y 1.3 3 V*, o. 43 V So, this branch operates with all -transistors in the active, region if H < 0.43 V 50 this lesion vvill u e the previous y cormputeef value .of

12 V

Figure 5.42 k -npn Darlington output stage. (c) Calculate the maximum average power that can be delivered to RL 8 ft before clipping occurs and the corresponding efficiency of the complete circuit. Also calculate the maximum instantaneous power dissipated in each output transistor. Assume that feedback is used around the circuit so that V0 is approximately sinusoidal. (d) Use SPICE to plot the dc transfer characteristic from Vj to V as V0 is varied over the complete output voltage range with RL...

120

In this example, acmc is much larger than acm because the transconductance in (12.35) is much larger than the degenerated transconductance in (12.37). The CMFB loop uses negative feedback to make Voc VCM. If VCM changes by a small amount from its design value due to parameter variations in the circuit that generates Vcm, Kr Should change by an equal amount so that Voc tracks VCM. The ratio A Voc A VCM is the closed-loop small-signal gain of the CMFB loop, which from Fig. 12.12 is 1, Acmfb 88 1...

1252114 2661114 3302e14 1999114 2302e14 3061e15

1.4921-22 2.378e-20 2.302e-20 6.126e-22 2.302s-20 1.492s-22 1.2521-14 2.661s-14 3.3021-14 1.9991-14 2.302e-14 3.0611-15 1.492e-22 2.378e-20 2.302e-20 6.126e-22 2.302e-20 1.492e-22 1.252e-14 2.661e-14 3.302e-14 1.999e-14 2.3021-14 3.0612-15 0 sjbop 1.000e-04 -1.277e-14 -2.967e-14 1.277e+00 1.690e+00 -1.277e+00 7.000e-01 5.774e-01 6.000e-04 0. 7.7b1e-23 2.402e-20 2.302e-20 9.206e-22 2.302e-20 7.781e-23 1.176e-22 4.800e-20 4.604e-20 1.841e-21 4.604e-20 1.176e-22 1.000e-04 -1.277e-14 -2.967e-14...

1280 V

To reduce the TCF, the constant M in (4.249)-(4.252) is often trimmed at one temperature so that the band-gap output is set to a desired target voltage.19 In principle, the target voltage is given by (4.253). In practice, however, significant inaccuracy in (4.253) stems from an approximation in (4.244).20 As a result, the target voltage is usually determined experimentally by measuring the TCp directly for several samples of each band-gap reference in a given process.2122 This procedure reduces...

130

Fi-om Curvd A > A0 38,000 mil* eu ne B, A0 - 20,000 um C ijooo mit2- curve a,& j and d axe predicied by t-he quation. 5 nversdy proporfi'onal -to fhe 5 3 , N X 5 tbtf. propor-tionAlihj constant related +0 the i afer siy mort Spea'f cAlly, K 5 effective, or uiablr txrea on tant vtafer). By (2-S6) , -the cost per un if silicon h -tota thermal r sistante 19 att

14

Also, (W L)21 14 since M26 and M27 are matched. In the example in Section 9.4.3, a compensation capacitor of 3.2 pF provided a 45 phase margin for a feedback factor of unity and a 5-pF load. The DM half-circuits for this example with the independent voltage sources Vsi and Vs2 set to zero are shown in Fig. 12.21 a. Here, we have assumed that CL is much larger than the input capacitance of the CM-sense devices M21 -M2a The two feedback networks connect between the two half-circuits in this...

146

1.3.5 Dependence of Transistor Current Gain pF on Operating Conditions Although most first-order analyses of integrated circuits make the assumption that fiF is constant, this parameter does in fact depend on the operating conditions of the transistor. It was shown in Section 1.3.2, for example, that increasing the value of Vce increases Ic while producing little change in IB, and thus the effective of the transistor increases. In Section 1.3.4 it was shown that as VCe approaches the breakdown...

15

Equation 11.40 shows the output noise-voltage spectral density is 5.0 X 1015 V2 Hz at low frequencies, and it approaches 0.88 X 1015 V2 Hz at high frequencies. The major contributor to the output noise in this case is the source resistance Rs, follow by the base resistance of the transistor. The noise spectrum given by (11.40) is plotted in Fig. 11,19.

15 V

Figure 9.59 Input stages of an op amp. 9.25 Assuming that the zero has been moved to infinity, determine the maximum load capacitance that can be attached directly to the output of the circuit of Fig. 9.60 and still maintain a phase margin of 45 . Neglect all higher order poles except any due to the load capacitance. Use the value of W L obtained in Problem 9.23 for M9 with the bias circuit of Fig. 9.61. 9.26 Repeat Problem 9.25 except, for the op amp, use the aspect ratios, supply voltages,...

16

Die in integrated high-frequency communication circuits. There are no sources of noise in ideal capacitors or inductors. In practice, real components have parasitic resistance that does display noise as given by the thermal noise formulas of (11.4) and (11.5). In the case of integrated-circuit capacitors, the parasitic resistance usually consists of a small value in series with the capacitor. Parasitic resistance in inductors can be modeled by either series or shunt elements. The device...

17

Integrated Circuits Output Signals

Figure 5.35 Schematic of the top error amplifier and output transistor M Figure 5.35 Schematic of the top error amplifier and output transistor M Since Mi3 and Mu also form a current mirror, and since (W L) 4 (W L) 13, Substituting (5.131) and (5.132) into (5.133) gives , _ , (w l) 13 tail hie - 'bias + Since ID15 di6 when IDU )12, KSD14 VsDn (313 V gl Therefore, ignoring channel-length modulation, Substituting (5.130) into (5.136) and rearranging gives

1ocoec2 5000e03 Socoe03 7000803 60ooeo3 5000e03 1000103 3cooe03 2 Oooe03 1000e03

1.OOOE-03 2.OC0E-03 3.OOOE-03 1.C0OE-O3 5.OOOE-03 .OOOE-03 1.0005-33 9.00 jE-03 .003E-33 1,000 s-32 5.508-01-' 5.ISE-01 i 5.138-01 ' 5.3U-01 -5.318-01 5.288-01 ' -5.218-01 < S.UI-01 ' 1.568-01 I -58E-01 1.728+00-' 2 288+00 2.308+00 2.318+30 < 2.32E+00 2.33E+00 ' 2.31E+00 + 2 -34E+00 2.318+00 i 35E+C0- OPERATING POINT INFORMATION TN0M NODE VOLTAGE NOES 'VOLTAGE 0 2 1.779E+00 0 3 1.OOOE-03 0 4 0 5 0. 0 6 1.727E+00 0 9 0 9 2.396E+00 0 100 2.500E+00 0 200 BIPOLAR JUSCTIOH TRANSISTORS SUBCKT...

2 C

Taking the positive square root in the right-most formula in (9.70) yields a value that is larger than one. Adding this value to 1 gives a positive value for the term in parentheses subtracting this value from 1 gives a negative quantity with a smaller magnitude than the sum. Therefore, one zero is in the LHP and has a magnitude greater than gmi (2Cm2). The other zero is in the RHP and has a smaller magnitude than the LHP zero. As a result, the effect of the RHP zero is felt at a lower...

2 Cr

One disadvantage of the above method of compensation is that the value of C required is quite large (typically > 1000 pF) and cannot be realized on a monolithic chip. Many general-purpose op amps have unity-gain compensation included on the monolithic chip and require no further compensation from the user. (The sacrifice in bandwidth caused by this technique when using gain other than unity was described earlier.) In order to realize an internally compensated monolithic op amp, compensation...

2

Equation 11.134 shows that, in general, the total equivalent input noise voltage of a circuit is obtained by integrating the product of the input noise-voltage spectrum and the normalized voltage gain function. One last topic that should be mentioned in this section is the problem that occurs in calculating the flicker noise in direct-coupled amplifiers. Consider an amplifier with an input noise spectral density as shown in Fig. 11.44a and a voltage gain that extends down to dc and up to f 10...

20

And thus the collector-base resistance is r l0f30ro 10 X 100 X 20 kO 20 Mil The equivalent circuit with these parameter values is shown in Fig. 1.21. 1.4.8 Specification of Transistor Frequency Response The high-frequency gain of the transistor is controlled by the capacitive elements in the equivalent circuit of Fig. 1.20. The frequency capability of the transistor is most often specified in practice by determining the frequency where the magnitude of the short-circuit, common-emitter current...

20 40 6080100

Figure 2.29 Capacitance and depletion-layer width of an abrupt pn junction as a function of applied voltage and doping concentration on the lightly doped side of the junction11 where NB is the doping density in the epi material and VR is the reverse bias on the junction. The nomograph of Fig. 2.29 can also be used to determine the junction depletion-region width as a function of applied voltage, since this width is inversely proportional to the capacitance. The width in microns is given on the...

2124105 2000105 9025113 1048105

5.0001-14 9.8071-15 -8.9351-15 4.9931-14 -9.8071-01 -9.8071-01 9.10(1+00 -8.9721-01 -5.0001+00 -9.8071-01 -1.7951-09 -4.9931+00 -7.0001-01 -7.0001-01 7.0001-01 -7.0001-01 1.7951-09 -1.9721-01 s.9811-05 5.3891-04 -8.9351-15 4.1031-14 -5.0001-14 5.0001-14 9.0391-01 -9.8071-01 8.9351-01 -9.8071-01 8.9351-01 -4.1021+00 5.0001+00 -5.0001+00 7.0001-01 -7.0001-01 7.0001-01 -7.0001-01

23 High Voltage Bipolar Integrated Circuit Fabrication

Integrated-circuit fabrication techniques have changed dramatically since the invention of the basic planar process. This change has been driven by developments in photolithography, processing techniques, and also the trend to reduce power-supply voltages in many systems. Developments in photolithography have reduced the minimum feature size attainable from tens of microns to the submicron level. The precise control allowed by ion implantation has resulted in this technique becoming the...

25

Circuit for Problem 12.23. V0i t Vod(t and Voc(t)l What are Vn(t Vi2 t Vid(t and Vlc(t)7 12.22 The op amp in Problem 12.4 is used with the CMFB scheme shown in Fig. 12.17. The circuit is perfectly balanced except that the CM-sense resistors are mismatched with the upper resistor Rcs 10.1 kil and the lower resistor Rcs2 9.9 kfL Assume the source followers and the CM-sense amplifier are ideal with gains of unity. (a) Compute the gains acms and adm-cms in (12.106). (b) Compute the...

2596211 5374e14 6601211 4146e14 1601211 6102e15

1.0002*07 1.1221*07 1.258E+07 1.4122*07 1.584E+07 1.7788*07 1. 958*07 2.2388*07 2.5118*07 2.8188*07 3.1628*07 3.5488*07 3.9818*07 4.4 6E 07 5.0118*07 5.6238*07 6.3098*07 7.079B*07 7.9438*07 8.9122+07 9.9998*07 1.1228*0 1.25B8*0I 1.4128*0 1.5848*0 1.7788*08 1.9958*08 2.2388*08 2.5118*08 2.8188*0 3.1628*0 3.5488*08 3.9811*08 4.4668*08 5.0111*08 5.6238*08 6.3098*08 7.0798*08 7.9438*08 8.9128*0 9.9998*0 1.1228*09 1.2588*09 1.4128*09 1.5848*09 1.7718*09 1.9958+09 2.2388*09 -7.928+01 -7.828*01...

26

The gain magnitude at low frequency is thus 36.1 dB and the gain versus frequency on log scales is plotted in Fig. 7.8 for frequencies below and slightly above pi . 7.2.1.2 The MOS Differential Amplifier Differential-Mode Gain A MOS differential amplifier with resistive loads is shown in Fig. 7.9. The differentialmode (DM) ac half-circuit and the corresponding small-signal circuit are shown in Figs. 7.10a and 7.10b, respectively. For compactness, the factor of 1 2 has been omitted from the...

31

Since Vds3 Vd32, Vm y,32 Vtn, and (W L)3l (W L)32. This equation shows that Icm is dependent on the CM output voltage and independent of the differential output voltage because changes in the drain currents in M31 and M32 due to nonzero V* are equal in magnitude and opposite in sign. Therefore, these changes cancel when the drain currents are summed in (12.62). Applying KVL around the lower transistors A 30-M35 gives Vds3l Vds35 + Vgs33 - (12.63) Assuming that I0 33, we have Vgs30 V .33, and...

35 30 25 20 15 10 5

Figure 2.63 (a) Plan view and cross section of polysilicon resistor. resistor described in Section 2.6.2 and shown in Fig. 2.42. It displays large tolerance, high voltage coefficient, and high temperature coefficient relative to other types of resistors. Higher sheet resistance can be achieved by the addition of the pinching diffusion just as in the bipolar technology case. MOS Devices as Resistors. The MOS transistor biased in the triode region can be used in many circuits to perform the...

3600

Where the pole magnitudes are in radians per second. Equation 9.21 gives a unity-gain frequency where a(ja> ) 1 of 780 kHz. This is slightly below the design value of 1 MHz because the actual gain curve is 3 dB below the asymptote at the break frequency p . At 780 kHz the phase shift obtained from (9.21) is -139 instead of the desired -135 and this includes a contribution of -11 from pole p2. Although this result is close enough for most purposes, a phase margin of precisely 45 can be...

4

Figure 2.61 Typical variation of threshold voltage as a function of substrate bias for -channel devices with uniform channel doping (no channel implant) and with nonuniform channel doping resulting from threshold adjustment channel implant. Figure 2.61 Typical variation of threshold voltage as a function of substrate bias for -channel devices with uniform channel doping (no channel implant) and with nonuniform channel doping resulting from threshold adjustment channel implant. this value. The...

4232

Since pF co for an MOS transistor, beta helpers are not used in simple MOS current mirrors to reduce the systematic gain error. However, a beta-helper configuration can increase the bandwidth of MOS and bipolar current mirrors. 4.2.4 Simple Current Mirror with Degeneration 4.2.4.1 Bipolar The performance of the simple bipolar transistor current mirror of Fig. 4.6 can be improved by the addition of emitter degeneration as shown in Fig. 4.7 for a current mirror with two independent outputs. The...

4242

Source degeneration is rarely used in MOS current mirrors because, in effect, MOS transistors are inherently controlled resistors. Thus, matching in MOS current mirrors is improved simply by increasing the gate areas of the transistors.2'3'4 Furthermore, the output resistance can be increased by increasing the channel length. To increase the output resistance while keeping the current and VGS - Vt constant, the W L ratio must be held constant. Therefore, the channel width must be increased as...

4l

We can now compute the differential output voltage as Vod Vol - v02 VDD - IdlRD - VDD + ld2RD -(Md) Rd (3.163) Since Md 0 when Vid 0, (3.163) shows that Vod 0 when Vid 0 if Mi and M2 are identical and if identical resistors are connected to the drains of M and M2. This property allows direct coupling of cascaded MOS differential pairs, as in the bipolar case. 3.5.4 Introduction to the Small-Signal Analysis of Differential Amplifiers The features of interest in the performance of differential...

5

This diode has a saturation current of Figure 3.8 Large-signal equivalent circuit valid when the transistor is in the forward-active & Fh region. The saturation current of the equivalent base-emitter diode is is pf current flows other than the leakage current ICo As the input voltage is increased, the transistor enters the forward-active region, and the collector current is given by The equivalent circuit for the amplifier when the transistor operates in the forward-active region was derived...

500

Using (9.139) in (9.137) shows that given these data, the maximum possible improvement in slew rate by use of emitter resistors is a factor of 21 times. Finally, in this description of methods of slew-rate improvement, we mention the class AB input stage described by Hearn.20 In this technique, the small-signal transconductance of the input stage is left essentially unchanged, but the limit Ixm on the maximum current available for charging the compensation capacitor is greatly increased. This...

500eos 500e05

-5.00E-05 . -5.00E-05 -5.00E-05 < -5.C0E-05-. -5.00E-05 -5.005-05 . -S.00E-05 < -5.00E-05 -5.00E-05 -5.CCE-05 -5.0CE-05 -5.005-05 . -S. OOE-05 < -5.005-05-' -5.005-05 . -5.005-05 . -5.00E-05 . -5.005-05 -5.0CE-05 . -5.0CE-C5 -5.C0E-05 . -5 005-05 . -5.005-05 Slightly So that a 1 the i-ranzisfors in the output branch of a current-mirror using -the circuit operate inthe active r ftion

567

56.7 1.4 k _ TT56J + 19-6m In (8.209), the second term that includes J can be neglected whenever d < sc A 8ft . This condition usually holds at low frequencies because d is the forward signal transfer through a passive network, while A 2ft, is large because it includes the gain through the active device(s). For example, ignoring the d (l + < 3i) term in (8.216) gives A -19.7ki , which is close to the exact value. As the frequency increases, however, the gain provided by the transistors...

6

As a < e 0, and the gain of the switched-capacitor amplifier approaches CXIC2 as predicted in (6.28). As a result, the circuit gain is said to be parasitic insensitive to an extent that depends on the op-amp gain. One important parameter of the switched-capacitor amplifier shown in Fig. 6.9a is the minimum clock period. This period is divided into two main parts, one for each clock phase. The duration of 02 must be long enough for the op-amp output to reach and stay within a given level of...

6 V

Figure 8.51 Circuit diagram of the 733 wideband monolithic amplifier. 8.20 A commercial wideband monolithic feedback amplifier (the 733) is shown in Fig. 8.51. This consists of a local series-feedback stage feeding a two-stage shunt-shunt feedback amplifier. The current output of the input stage acts as a current drive to the shunt-shunt output stage. (a) Assuming all device areas are equal, calculate the collector bias current in each device. (b) Calculate input impedance, output impedance,...

6000e01 4595e01 8388e03 2670s01 3854e03 5185e05 5189e04

ID 1.066E-06 -1.066E-06 -1.000E-06 IBD -1.001E-14 1.999E-14 6.156E-15 VGS 6.094E-01 -6.156E-01 -6.1S6E-01 VDS 1.001E+00 -1.998E+00 -6.156E-01 VTH 6.000E-01 -6.000E-01 - .000E-01 VDSAT 9.380E-03 -1.565E-02 -1.565E-02 BETA 2.423E-02 8.703E-03 8.166E-03 GM 2.272E-04 1.362E-04 1.278E-04 GDS 2.498E-08 4.757E-08 4.7S7E-08 SMALL-SIGNAL TRANSFER CHARACTERISTICS INPUT RESISTANCE AT VI 1.000E+20 OUTPUT RESISTANCE AT V(2) 1.378E+07 SMALL-SIGNAL TRANSFER CHARACTERISTICS INPUT RESISTANCE AT VI 1.000E+20...

6210Operational Amplifier Equivalent Circuit

The effect of some of these deviations from ideality on the low-frequency performance of an op amp in a particular application can be calculated using the equivalent circuit shown in Fig. 6.14. (This model does not include the effects of finite PSRR or CMRR.) Here, the two current sources labeled bias represent the average value of dc current flowing into the input terminals. The polarity of these current sources shown in Fig. 6.14 applies for an npn transistor input stage. The current source...

622 Input Offset Current

For the emitter-coupled pair shown in Fig. 6.11, the two input bias currents will be equal only if the two transistors have equal betas. Geometrically identical devices on the same IC die typically display beta mismatches that are described by a normal distribution with a standard deviation of a few percent of the mean value. Since this mismatch in the two currents varies randomly from circuit to circuit, it cannot be compensated by a fixed resistor. This aspect of op-amp performance is...

623Input Offset Voltage

As described in Chapter 3, mismatches result in nonzero input offset voltage in amplifiers. The input offset voltage is the differential input voltage that must bfej& pplied to drive ,the output to zero. For uritrimmed mohbllthic op ampsTthis offset is typically 0.1 to 2 raV for bipolar input devices and 1 to 20 mV for MOS input devices. This offset can be nulled with an external potentiometer in the case of stand-alone op amps however, the variation of offset with temperature (called drift)...

625Common Mode Rejection Ratio CMRR

If an op amp has a differential input and a single-ended output, its small-signal output voltage can be described in terms of its differential and common-mode input voltages vid and vu) by the following equation where Adm is the differential-mode gain and Acm is the common-mode gain. As defined in (3.187), the common-mode rejection ratio of the op amp is From an applications standpoint, the CMRR can be regardedas_the_ hange in input offset voltage that results from a unit change in common-mode...

626

9.4.1 Theory of Compensation 633 9.4.2 Methods of Compensation 637 9.4.3 Two-Stage MOS Amplifier Compensation 644 9.4.4 Compensation of Single-Stage CMOS OP Amps 652 9.4.5 Nested Miller Compensation 656 9.5.1 Root Locus for a Three-Pole Transfer Function 664 9.5.2 Rules for Root-Locus Construction 667 9.5.3 Root Locus for Dominant-Pole Compensation 675 9.5.4 Root Locus for Feedback-Zero Compensation 676 9.6.1 Origin of Slew-Rate Limitations 680 9.6.2 Methods of Improving Slew-Rate 684 9.6.3...

63 Basic Two Stage MOS Operational Amplifiers

Figure 6.15 shows a schematic of a basic two-stage CMOS op amp.4 5-6 A differential input ctdfTA nrttroc o f . 11------1 l______i ----o -- jti uiuwviiLiai input stage drives an active load followed by a second gain stage. An output stage is usually not - -------j wwv,. & clin -vu uutjjui suige is usuauy not used but may be added for driving heavy loads off-chip. This circuit configuration provides good common-mode range, output swing, voltage gain, and CMRR in a simple circuit that Figure...

631 Input Resistance Output Resistance and Open Circuit Voltage Gain

The first stage in Fig. 6.16 consists of a -channel differential pair M -Mi with an n-channel current mirror load M3-M4 and a -channel tail current-source The second stage consists of an -channel common-source amplifier M(, with a -channel current-source load M7. Because the op-amp inputs are connected to the gates of MOS transistors, the input resistance is essentially infinite when the op amp is used in internal applications, which do not require the protection diodes described in Section...

633Input Offset Voltage

In Sections 3.5.6 and 6.2.3, the input offset voltage of a differential amplifier was defined as the differential input voltage for which the differential output voltage is zero. Because the op amp in Fig. 6.16 has a single-ended output, this definition must be modified here. Referring to the voltage between the output node and ground as the output voltage, the most straightforward modification is to define the input offset voltage of the op amp as the differential input voltage for which the...

635 Common Mode Input Range

The common-mode input range is the range of dc common-mode input voltages for which all transistors in the first stage of the op amp operate in the active region. To operate in the active region, the gate-drain voltages of -channel transistors must be less than their thresholds so that their channels do not exist at their drains. Similarly, p-channel transistors operate in the active region only if their gate-drain voltages are more than their thresholds, again so that their channels do not...

636 Power Supply Rejection Ratio PSRR

To calculate the PSRR from the Vdd supply for the op amp in Fig. 6.16, we will divide the small-signal gain A+ v0 vdd into the gain from the input. For this calculation, assume that the Vss supply voltage is constant and that both op-amp inputs in Fig. 6.16 are connected to small-signal grounds. The current in M8 is equal to bias- If this current is constant, the gate-source voltage of M must be constant because M8 is diode connected. Therefore, v,,vX vgsl 0, and the gm generators in M5 and M7...

637Effect of Overdrive Voltages

The overdrive of a MOS transistor can be reduced by reducing the ratio of its drain current to its W L, Reducing the overdrive voltages in the op amp in Fig. 6.16 improves the op-amp performance by increasing the voltage gain as shown by (6.59), increasing the swing as shown by (6.61), reducing the input offset voltage as shown by (6.69), increasing the CMRR as shown by (6.72), increasing the common-mode range as shown by (6.78), and increasing the power-supply rejection ratio as shown by...

638Layout Considerations

A basic objective in op-amp design is to minimize the mismatch between the two signal paths in the input differential pair so that common-mode input signals are rejected to the greatest possible extent. Mismatch affects the performance of the differential pair not only at dc, where it causes nonzero offset voltage, but also at high frequencies where it reduces the common-mode and power-supply rejection ratios. Figure 6.22a shows a possible layout of a differential pair. Five nodes are labeled...

66 MOS Folded Cascode Operational Amplifiers

Figure 6.26 shows two cascode circuits where VDD 0 for simplicity. In Fig. 6.26a, both Mi and Mm are p-channe devices. In Fig. 6.26b, M is still a p-channel device but M A Figure 6.26 shows two cascode circuits where VDD 0 for simplicity. In Fig. 6.26a, both Mi and Mm are p-channe devices. In Fig. 6.26b, M is still a p-channel device but M A Figure 6.26 (a) Standard cascode configuration. (b) Folded-cascode configuration. is now an -channel device. In both cases, however, M is connected in a...

67 MOS Active Cascode Operational Amplifiers

One way to increase the gain of the folded-cascode op amp without cascading additional stages is to add another layer of cascodes. See Problem 6.21. Although this approach gives a gain on the order of (gmr0)3, it reduces the output swing by at least another overdrive in each direction. This reduction becomes increasingly important as the difference between the power-supply voltages is reduced in scaled technologies. To increase the op-amp gain without reducing the output swing, the...

681 The dc Analysis of the 741 Operational Amplifier

The first step in evaluating the performance of the circuit is to determine the quiescent operating current and voltage of each of the transistors in the circuit. This dc analysis presents a special problem in op-amp circuits because of the very high gain involved. If we were to begin the dc analysis with the assumption that the two input terminals are grounded and then try to predict the output voltage, we would find that a small variation in the beta or output resistance of the devices in the...

682 Small Signal Analysis of the 741 Operational Amplifier

Our next objective is to determine the small-signal properties of the amplifier. We will break the circuit up into its three stages the input stage, gain stage, and output stage and determine the input resistance, output resistance, and transconductance of each stage. Consider first the ac schematic of the input stage as shown in Fig. 6.37. Here we have assumed a pure differential-mode input to the circuit we will consider common-mode inputs later. As a result, the collectors of Q and < 22 as...

69 Design Considerations for Bipolar Monolithic Operational Amplifiers

Operational-amplifier design involves trade-offs between the various dc, small-signal, and transient performance parameters as well as the die size and resultant cost. In the 741, the principal design objective was to obtain an internally compensated circuit with moderate dc and ac performance while maintaining a small inexpensive die. However, by the use of more complex circuitry, the dc, small-signal, and transient performance of the circuit can be greatly improved. Frequently, steps taken to...

691 Design of Low Drift Operational Amplifiers

The offset voltage of multistage differential amplifiers depends primarily on the offset of the first stage, provided that the stage has sufficiently high voltage gain. Thus the design of low-offset amplifiers is primarily a problem of designing an input stage in which as few component pairs as possible contribute to the stage offset voltage. In the 741, the input stage is relatively complicated since it provides gain, level shifting, and differential-to-single-ended conversion. A more optimum...

692 Design of Low InputCurrent Operational Amplifiers

In instrumentation applications in which the signal source has a low internal impedance, the input offset voltage and its associated drift usually place a lower limit on the dc voltage than can be resolved. When the source impedance is high, however, the input bias current and input offset current of the op amp flowing in the source resistance or the gain-setting resistors can be important in limiting the ability of the circuit to resolve small dc signals. Furthermore, many applications involve...

7

Thus the transfer characteristic of the feedback amplifier of Fig. 8.3 shows much less nonlinearity than the original basic-amplifier characteristics of Fig. 8.2. Note that the horizontal scale in Fig. 8.3 has been compressed as compared to Fig. 8.2 in order to allow easy comparison of the two graphs. This scale change is necessary because Figure 8.3 Feedback-amplifier transfer characteristic corresponding to the basic-amplifier characteristic of Fig. 8.2. the negative feedback reduces the...

70000e01 60000101 50000e01 40000101 30000e01 20000b01 10000e01

1.0000E-01 2.00001-01 3.0000E-01 4.0000E-01 5.0000B-01 6.0000E-01 7.0000E-01 .00001-01 9.0000E-01 1.0000E+00 1.1000E+00 1.20001+00 1.3000E+00 1.4000E+00 1.5000E+00 1. OOOE+OO 1.7000E+00 1.8000E+00 1.9000E+00 2.0000E+00 2.1000E+00 2.2000E+00 2.3000E+00 2.4000E+00 2.5000E+00 VOLTAGE 17 200 1.327E+00 1.1818+00 9.983E-01 9.2748-01 9.247E-01 9.221E-01 9.196E-01 9.1718-01 9.1451-01 9.120E-01 9.095E-01 9.070E-01 9.0441-01 9.019E-01 8.9941-01 8.969E-01 I.944E-01 8.919E-01 8.894E-01 8.869E-01 8.844E-01...

7143e01 7291e05 8810e06 9318e06 1470e06 3794e06 3921106 4792e06 1316e05

1.000E+00 1.021E-04 1.233E-05 1.304E-05 2.058E-06 5.312E-06 5.489E-06 6.708E-06 1.842E-05 1.764E+02 8.825E+01 9.282E+01 8.5612+01 1.0241+02 7.440E+01 4.849E+00 9.9021+01 1.7471+02 -8.8141+01 -8.357E+01 -2.620E+02 -2.788E+02 -1.0201+02 -1.7151+02 -7.7381+01 -3.5111+02 TOTAL HARMOanC DISTORTIOH 1.058E-02 FERCEHT FOURIER COMPOHEHTS OF TRAHSIZHT RESPONSE V(9,10) DC COKPOHEHT - 1.793D+00 HARMCNIC FREQUEHCT FOURIER NORMALIZED PHASE NORMALIZED HO (HZ) COSIPOBttHT COKFCNEHT (DEG) PHASE (DEG)

72 Single Stage Amplifiers

The basic topology of the small-signal equivalent circuits of bipolar and MOS single-stage amplifiers are similar. Therefore in the following sections, the frequency-response analysis for each type of single-stage circuit is initially carried out using a general small-signal model that applies to both types of transistors, and the general results are then applied to each type of transistor. The general small-signal transistor model is shown in Fig. 7.1. Table 7.1 lists the parameters of this...

73 Multistage Amplifier Frequency Response

The above analysis of the frequency behavior of single-stage circuits indicates the complexity that can arise even with simple circuits. The complete analysis of the frequency response of multistage circuits with many capacitive elements rapidly becomes very difficult and the answers become so complicated that little use can be made of the results. For this reason approximate methods of analysis have been developed to aid in the circuit design phase, and computer simulation is used to verify...

75 Relation Between Frequency Response and Time Response

In this chapter the effect of increasing signal frequency on circuit performance has been illustrated by considering the circuit response to a sinusoidal input signal. In practice, however, an amplifier may be required to amplify nonsinusoidal signals such as pulse trains or square waves. In addition, such signals are often used in testing circuit frequency response. The response of a circuit to such input signals is thus of some interest and will now be calculated. Initially we consider a...

783

Common centroid geometry, 440-442, 476,477 configuration, 202 Common-collector-common-emitter configuration, 202 Common-collector configuration, 191, 503 Common-drain configuration, 195, 509, 591 Common-emitter-common-base configuration, see Cascode configuration Common-emitter configuration, 175, 490, 494 Common-emitter frequency response, 490, 494 Common-emitter output stage, 576 Common-gate configuration, 186, 188, 190.515, 525 Common-gate frequency response, 515 Common-mode feedback, 228,...

7t

Where Rc is the collector resistor in the Gilbert multiplier and gm is the transconduc-tance of the transistors. The phase detector output voltage then becomes proportional to the amplitude V, of the incoming signal, and if the signal amplitude varies, then the loop gain of the phase-locked loop changes. Thus when the signal amplitude varies, it is often necessary to precede the phase detector with an amplifier limiter to avoid this problem. In FM demodulators, for example, any amplitude...

8 9

Figure 9.49 Response of the circuit of Fig. 9.48 when a 5-V step input is applied, (a) Response predicted by (9.125) for the 741 op amp. (b) Measured response for the 741. The current from the input stage, which charges the compensation capacitor, is lx. The large-signal transfer characteristic from the op-amp differential input voltage Vid to Ix is that of a differential pair, which is shown in Fig. 9.51. From Fig. 9.51, the maximum current available to charge C is 211, which is the tail...

81 Ideal Feedback Equation

Consider the idealized feedback configuration of Fig. 8.1. In this figure 5, and SQ are input and output signals that may be voltages or currents. The feedback network (which is usually linear and passive) has a transfer function and feeds back a signal Sfb to the input. At the input, signal Sfb is subtracted from input signal at the input differencing node. Error signal Se is the difference between St and Sfb, and S is fed to the basic amplifier with transfer function a. Note that another...

82 945

48.4V,- (rad)1 (10.100) where V is the peak amplitude of the sinusoidal input. In terms of the rms value, Thus for a 1-mV rms input, for example, the value of KD is equal to 0.068 V rad. We now analyze the voltage-controlled oscillator shown in Fig. 10.29. We initially assume that the input differential voltage is zero, so the four emitter-coupled transistors (035 to 03g) all conduct the same current. The collector currents of Qyi and C 38 are thus 125 jjlA, and the total current flowing from...

841 Series Shunt Feedback

Suppose it is required to design a feedback amplifier that stabilizes a voltage transfer function. That is, a given input voltage should produce a well-defined proportional output voltage. This will require sampling the output voltage and feeding back a proportional voltage for comparison with the incoming voltage. This situation is shown schematically in Fig. 8.4. The basic amplifier has gain a, and the feedback network is a two-port with transfer function that shunts the output of the basic...

843 Shunt Series Feedback

The shunt-series configuration is shown in Fig. 8.11. The feedback network samples ia and feeds back a proportional current ifb fiD. Since the desired output signal is a current i0, it is more convenient to represent the output of the basic amplifier with a Norton equivalent. In this case both a and are dimensionless current ratios, and the ideal input source is a 8,5 Practical Configurations and the Effect of Loading 563 Basic amplifier 8,5 Practical Configurations and the Effect of Loading...

85 Practical Configurations and the Effect of Loading

In practical feedback amplifiers, the feedback network causes loading at the input and output of the basic amplifier, and the division into basic amplifier and feedback network is not as obvious as the above treatment implies. In such cases, the circuit can always be analyzed by writing circuit equations for the whole amplifier and solving for the transfer function and terminal impedances. However, this procedure becomes very tedious and difficult in most practical cases, and the equations so...

851 Shunt Shunt Feedback

Consider the shunt-shunt feedback amplifier of Fig. 8.9. The effect of nonideal networks may be included as shown in Fig. 8.13a, where finite input and output admittances are assumed in both forward and feedback paths, as well as reverse transmission in each. Finite source and load admittances ys and yL are assumed. The most convenient two-port Figure 8.13 (a) Shunt-shunt feedback configuration using the y-parameter representation, (b) Circuit of (a) redrawn with generators _y2i v,- and y 2av0...

852 Series Series Feedback

Consider the series-series feedback connection of Fig. 8.12. The effect of nonideal networks can be calculated using the representation of Fig. 8.16 . In this case the most convenient two-port representation is the use of the open-circuit impedance parameters or z parameters because the basic amplifier and the feedback network are now connected in series at input and output and thus have identical currents at their terminals. As shown in Fig. 8.17, the z parameters specify the network by...

853 Series Shunt Feedback

Series-shunt feedback is shown schematically in Fig. 8.4. The basic amplifier and the feedback network have the same input current and the same output voltage. A two-port representation that uses input current and output voltage as the independent variables is the hybrid -parameter representation shown in Fig. 8.22. The h parameters can be used to represent nonideal circuits in a series-shunt feedback as shown in Fig. 8.23a. Summation of voltages at the input of this figure gives Vs (zs + hUa +...

854 Shunt Series Feedback

Shunt-series feedback is shown schematically in Fig. 8.11. In this case the basic amplifier and the feedback network have common input voltages and output currents, and hybrid g parameters as defined in Fig. 8.29 are best suited for use in this case. The feedback circuit is shown in Fig. 8.30a, and, at the input, we find that (ys + glla + gllf)Vi + (gl 2 + g 12 f)io node, and the feedback function can be identified as The gain a of the basic amplifier is determined by calculating the current...

86 Single Stage Feedback

The considerations of feedback circuits in this chapter have been mainly directed toward the general case of circuits with multiple stages in the basic amplifier. However, in dealing with some of these circuits (such as the series-series triple of Fig. 8.18a), equivalent circuits were derived in which one or more stages contained an emitter resistor. (See Fig. 8.18c.) Such a stage represents in itself a feedback circuit as will be shown. Thus the circuit of Fig. 8.18c contains feedback loops...

87 The Voltage Regulator as a Feedback Circuit

As an example of a practical feedback circuit, the operation of a voltage regulator will be examined. This section is introduced for the dual purpose of illustrating the use of feedback in practice and for describing the elements of voltage regulator design. Voltage regulators are widely used components that accept a poorly specified (possibly fluctuating) dc input voltage and produce from it a constant, well-specified output voltage that can then be used as a supply voltage for other...