02

Figure 4.59 Cascode active-load circuit for Problem 4.16. Figure 4.59 Cascode active-load circuit for Problem 4.16. drwn 1 ixm and Xd 0. Use Table 2.3 for other parameters. 4.15 Repeat Problem 4.14, but now assuming that 2 kil resistors are inserted in series with the sources of M3 and M4. Ignore the body effect. 4.16 Determine the unloaded voltage gain v0 v, and output resistance for the circuit of Fig. 4.59. Neglect Verify with SPICE and also use SPICE to plot the large-signal Vq-Vi transfer...

03

Figure 5.18 Simplified schematic of the output stage of the 709 op amp. The limiting values that Va can take are determined by the driver stage. When V, is taken large positive, V decreases until saturates, at which point the negative voltage limit V is reached y o -VCC + VC 3(sat) Vbe2 (5.76) For values of Vx between ( VCc + C 3 sat)) and (- VBE(on)), both Q3 and Q2 are in the forward-active region, and V0 follows V with Q2 acting as an emitter follower. As Vi is taken negative, the current in...

05

Figure 2.30 Typical parameters for high-voltage integrated npn transistors with 500 fxm2 emitter area. The thick epi device is typical of those used in circuits operating at up to 44 V power-supply voltage, while the thinner device can operate up to about 20 V. While the geometry of the thin epi device is smaller, the collector-base capacitance is larger because of the heavier epi doping. The emitter-base capacitance is higher because the base is shallower, and the doping level in the base at...

082 082

This calculation assumes that dXd dVDS and Leff are constant for each type of transistor, allowing us to use constant Early voltages. In practice, however, dXd dVDS and Leff both depend on the operating point, and accurate values of the Early voltages are rarely available to circuit designers when channel lengths are less than about 1.5 xm. As a result, circuit simulations are an important part of the design process. SPICE simulation of the op amp under the conditions described above gives a...

09

Compare your answer with a SPICE simulation. Also, compare your answer to the result that would apply without mismatch. 4.19 Although Gm cni of a differential pair with a current-mirror load can be calculated exactly from a small-signal diagram where mismatch is allowed, the calculation is complicated because the mismatch terms interact, and the results are difficult to interpret. In practice, the mismatch terms are often a small fraction of the corresponding average values, and the...

1

The validity of (1.51) depends on W2Bl2TbDn 1 and (Dp Dn)(WB Lp)(NA ND) < sc 1, and this is always true if 3F is large see (1.48) . The term y in (1.51) is called the emitter injection efficiency and is equal to the ratio of the electron current (npn transistor) injected into the base from the emitter to the total hole and electron current crossing the base-emitter junction. Ideally y 1, and this is achieved by making ND NA large and WB small. In that case very little reverse injection occurs...

1 1

Equation 3.84 shows that the body effect reduces the output resistance, which is desirable because the source follower produces a voltage output. This beneficial effect stems from the nonzero small-signal current conducted by the gmb generator in Fig. 3.25b, which increases the output current for a given change in the output voltage. As ra oo and Rl oo, this output resistance approaches l (gm + gmb). The common-gate input resistance given in (3.54) approaches the same limiting value. As with...

1 1 1

Figure 9.45 Poles of the transfer function of the feedback amplifier of Fig. 9.41. The transfer function contains no zeros. near the jco axis, which would give rise to an excessively peaked response. In practice, oscillation can occur because higher magnitude poles do exist and these would tend to give a locus of the kind of Fig. 9.39, where the remote poles cause the locus to bend and enter the right half-plane. (Note that this behavior is consistent with the alternative approach of...

10

Allowed dimensions of passive devices have also decreased.) This trend is driven primarily by economics in that reducing dimensions increases the number of devices and circuits that can be processed at one time on a given wafer. A second benefit has been that the frequency capability of the active devices continues to increase, as intrinsic fj values increase with smaller dimensions while parasitic capacitances decrease. Vertical dimensions such as the base width of a bipolar transistor in...

10 V

Figure 11.54 Differential-pair input stage for Problem 11.14. figure of this circuit in decibels for 10 kft using the following data. Neglect flicker noise and capacitive effects. (b) If the device has fT 500 MHz, calculate the frequency where the noise figure is 3 dB above its low-frequency value. 11.20 (a) Neglecting capacitive effects, calculate the noise figure in decibels of the circuit of Fig. 11.52 with Rs 5 kft. Use data as in Problem 11.10. (b) If the flicker noise corner frequency for...

100

V2 v0- Vbe20 (10 - 0.525) V 9.475 V Vi v2 - Vbe23 (9.475 - 0.613) V 8.862 V 5.4.4 All-npn Class B Output Stage7-6-9 The Class B circuits described above are adequate for many integrated-circuit applications where the output power to be delivered to the load is of the order of several hundred milliwatts or less. However, if output-power levels of several watts or more are required, these circuits are inadequate because the substrate pnp transistors used in the output stage have a limited...

101

3.3.7 Common-Drain Configuration (Source Follower) The common-drain configuration is shown in Fig. 3.25a. The input signal is applied to the gate and the output is taken from the source. From a large-signal standpoint, the output voltage is equal to the input voltage minus the gate-source voltage. The gate-source voltage consists of two parts the threshold and the overdrive. If both parts are constant, the resulting output voltage is simply offset from the input, and the small-signal gain would...

102 Precision Rectification

Perhaps the most basic nonlinear operation performed on time-varying signals is rectification. An ideal half-wave rectifier is a circuit that passes signal currents or voltages of only one polarity while blocking signal voltages or currents of the other polarity. The transfer characteristic of an ideal half-wave rectifier is shown in Fig. 10.1. Also shown in Fig. 10.1 is the transfer characteristic of a second useful rectifier, the full-wave type. Practical rectifiers can be divided into two...

1034 A Complete Analog Multiplier3

In order to be useful in a wide variety of applications, the multiplier circuit must develop an output voltage that is referenced to ground and can take on both positive and negative values. The transistors Q3, Q4, Q5, Q6, Q7t and 8, shown in Fig. 10.13, are referred to as the multiplier core and produce a differential current output that then must be amplified, converted to a single-ended signal, and referenced to ground. An output amplifier is thus required, and the complete multiplier...

1035 The Gilbert Multiplier Cell as a Balanced Modulator and Phase Detector

The four-quadrant multiplier just described is an example of an application of the multiplier cell in which all the devices remain in the active region during normal operation. Used in this way the circuit is capable of performing precise multiplication of one continuously varying analog signal by another. In communications systems, however, the need frequently arises for the multiplication of a continuously varying signal by a square wave. This is easily accomplished with the multiplier...

104 Phase Locked Loops PLL

The phase-locked loop concept was first developed in the 1930s.4 It has since been used in communications systems of many types, particularly in satellite communications systems. Until recently, however, phase-locked systems have been too complex and costly for use in most consumer and industrial systems, where performance requirements are more modest and other approaches are more economical. The PLL is particularly amenable to monolithic construction, however, and integrated-circuit...

1041 Phase Locked Loop Concepts

A block diagram of the basic phase-locked loop system is shown in Fig. 10.18. The elements of the system are a phase comparator, a loop filter, an amplifier, and a voltage-controlled oscillator. The voltage-controlled oscillator, or VCO, is simply an oscillator whose frequency is proportional to an externally applied voltage. When the loop is locked on an incoming periodic signal, the VCO frequency is exactly equal to that of the incoming signal. The phase detector produces a dc or...

1042 The Phase Locked Loop in the Locked Condition

Under locked conditions, a linear relationship exists between the output voltage of the phase detector and the phase difference between the VCO and the incoming signal. This fact allows the loop to be analyzed using standard linear feedback concepts when in the locked condition. A block diagram representation of the system in this mode is shown in Fig. 10.20. The gain of the phase comparator is KD V rad of phase difference, the loopfilter transfer function is F(s), and any gain in the forward...

11

Note that both (1.21) and (1.22) predict values of Cj approaching infinity as Vd approaches i o- However, the current flow in the diode is then appreciable and the equations no longer valid. A more exact analysis2 3 of the behavior of Cj as a function of Vd gives the result shown in Fig. 1.3. For forward bias voltages up to about i y0 2, the values of C predicted by (1.21) are very close to the more accurate value. As an approximation, some computer programs approximate Cj for VD > < 0 2 by...

111

Figure 10.15 Input and output spectra for a balanced modulator. This dc component can be introduced intentionally to provide conventional amplitude modulation or it can be the result of offset voltages in the devices within the modulator, which results in undesired carrier feedthrough in suppressed-carrier modulators. Note that the balanced modulator actually performs a frequency translation. Information contained in the modulating signal Vm(t) was originally concentrated at the modulating...

1115

Check headroom requirements in the bias circuit For the. branch induct ing M,3 0, this branch operate with all transistors in the active region if Voy C 0-33 V For the branch including M 0.1 v) - VT in 4- 0.7 v- (-ifc). 0 U,. in 4 36 mV (neglect) - -0.8 V 5 -0. -0 -0 -0.7-(-l'5) 3 y 1.3 3 V*, o. 43 V So, this branch operates with all -transistors in the active, region if H < 0.43 V 50 this lesion vvill u e the previous y cormputeef value .of

116

Thus, for stability, the Nyquist criterion requires that T0 < 11.6 and this is close to the answer obtained from the root locus. If the point on the jw axis where the root locus crossed had been determined more accurately, it would have been found to be at 3.8 x 106 rad s and both methods would predict instability for T0 > 11.6. It should be pointed out that the root locus for Fig. 9.39 shows the movement of the poles of the feedback amplifier as T0 changes. The theory developed in Section...

12 V

Figure 5.42 k -npn Darlington output stage. (c) Calculate the maximum average power that can be delivered to RL 8 ft before clipping occurs and the corresponding efficiency of the complete circuit. Also calculate the maximum instantaneous power dissipated in each output transistor. Assume that feedback is used around the circuit so that V0 is approximately sinusoidal. (d) Use SPICE to plot the dc transfer characteristic from Vj to V as V0 is varied over the complete output voltage range with RL...

120

In this example, acmc is much larger than acm because the transconductance in (12.35) is much larger than the degenerated transconductance in (12.37). The CMFB loop uses negative feedback to make Voc VCM. If VCM changes by a small amount from its design value due to parameter variations in the circuit that generates Vcm, Kr Should change by an equal amount so that Voc tracks VCM. The ratio A Voc A VCM is the closed-loop small-signal gain of the CMFB loop, which from Fig. 12.12 is 1, Acmfb 88 1...

1252114 2661114 3302e14 1999114 2302e14 3061e15

1.4921-22 2.378e-20 2.302e-20 6.126e-22 2.302s-20 1.492s-22 1.2521-14 2.661s-14 3.3021-14 1.9991-14 2.302e-14 3.0611-15 1.492e-22 2.378e-20 2.302e-20 6.126e-22 2.302e-20 1.492e-22 1.252e-14 2.661e-14 3.302e-14 1.999e-14 2.3021-14 3.0612-15 0 sjbop 1.000e-04 -1.277e-14 -2.967e-14 1.277e+00 1.690e+00 -1.277e+00 7.000e-01 5.774e-01 6.000e-04 0. 7.7b1e-23 2.402e-20 2.302e-20 9.206e-22 2.302e-20 7.781e-23 1.176e-22 4.800e-20 4.604e-20 1.841e-21 4.604e-20 1.176e-22 1.000e-04 -1.277e-14 -2.967e-14...

1280 V

To reduce the TCF, the constant M in (4.249)-(4.252) is often trimmed at one temperature so that the band-gap output is set to a desired target voltage.19 In principle, the target voltage is given by (4.253). In practice, however, significant inaccuracy in (4.253) stems from an approximation in (4.244).20 As a result, the target voltage is usually determined experimentally by measuring the TCp directly for several samples of each band-gap reference in a given process.2122 This procedure reduces...

130

Fi-om Curvd A > A0 38,000 mil* eu ne B, A0 - 20,000 um C ijooo mit2- curve a,& j and d axe predicied by t-he quation. 5 nversdy proporfi'onal -to fhe 5 3 , N X 5 tbtf. propor-tionAlihj constant related +0 the i afer siy mort Spea'f cAlly, K 5 effective, or uiablr txrea on tant vtafer). By (2-S6) , -the cost per un if silicon h -tota thermal r sistante 19 att

131

CK 1.449E-13 1.70 E-13 1.7068-13 1.449E-13 CCS 5.7951-13 7.359E-13 7.3591-13 5.795E-13 BETMC 2.000E+02 2.000E+02 2.000E+02 2.000E+02 PT 7.747E+06 2.071E+08 2.071E+08 7.747E+06 IC HttLTSIS THOH 27.000 TEUF* 27.000 (A I -2.0008*01 0. 2.000B*01 1.0008*01 6.000E 01 9.9998*03 3 1.2581*0 3.798*01 ****** A*** 1.5818*0 3.798*01 ****** A*** 1.9958*0 3.798*01 ** A 2.5118*01 3.798*01 ****** A + * 3.9818*01 3 .798*01 ****** A+* 5.0118*0 3.798*01 ****** A* + * 6.3098*0 3.798*01 ****** A*** 1.0008*05...

14

Also, (W L)21 14 since M26 and M27 are matched. In the example in Section 9.4.3, a compensation capacitor of 3.2 pF provided a 45 phase margin for a feedback factor of unity and a 5-pF load. The DM half-circuits for this example with the independent voltage sources Vsi and Vs2 set to zero are shown in Fig. 12.21 a. Here, we have assumed that CL is much larger than the input capacitance of the CM-sense devices M21 -M2a The two feedback networks connect between the two half-circuits in this...

1401118

1.3071-15 sq v hz * 3.615e-08 v rt hz 2.8981+00 -2.1231+00 -2.999e+00 2.907e-03 1.000e+02 3.867e-02 2.586e+03 1.000e+02 2.124e+16 5.605e-13 3.209e-14 0. 0. model id ibs xbd vgs vds vbs vth vdsat beta gam eff 2.931e-03 -8.7621-15 -5.000e-14 1.6881+00 4.1231+00 -8.7621-01 7.0001-01 9.8841-01 6.000e-03 0. 1.241e-15 1.549e-13 1.8501-13 3.7721-14 1.5051-13 1.2411-15 total output boise voltage 4.7861-17 sq v hz 6.9181-09 v rt hz v(5) vi equivali ihput boise at vi freq*7.5ghz equivaleht ihput boise...

146

1.3.5 Dependence of Transistor Current Gain pF on Operating Conditions Although most first-order analyses of integrated circuits make the assumption that fiF is constant, this parameter does in fact depend on the operating conditions of the transistor. It was shown in Section 1.3.2, for example, that increasing the value of Vce increases Ic while producing little change in IB, and thus the effective of the transistor increases. In Section 1.3.4 it was shown that as VCe approaches the breakdown...

15

KMXL PHPA PHP ET-50 ISaO.51-15 VA7-50 .UD PHPB PHP BF-50 IS-1.5E-15 VAF-50 OPTIOHS NOPAGX NQMOD ASSUVHX3 VCE(SAT) - 0.2 V MS) VBE(OM) 0.7 V, THE HAND CALCULATIONS PREDICT A COMMON-NODE RANGE Or -12.7 V < VIC < 14. V Of THE VOLTAGE- FOLLOWER CCKTIOtrRATTOR, VO VI VIC AS LOOS AS THE AMPLIFIER IS WORKING CORRECTLY. THE RESULTS ot THIS SIMULATION SHOW THAT VO VI FOR THE FOLLCMING RANGE THEREFORE, THIS SIMULATION SHOWS THAT THE -13 V < (VO a VI a VIC) < 14.5 V MHICH IS CLOSE TO THE RESULT...

15 V

Figure 9.59 Input stages of an op amp. 9.25 Assuming that the zero has been moved to infinity, determine the maximum load capacitance that can be attached directly to the output of the circuit of Fig. 9.60 and still maintain a phase margin of 45 . Neglect all higher order poles except any due to the load capacitance. Use the value of W L obtained in Problem 9.23 for M9 with the bias circuit of Fig. 9.61. 9.26 Repeat Problem 9.25 except, for the op amp, use the aspect ratios, supply voltages,...

16

This equation shows that the second-harmonic distortion can be reduced by increasing the dc output voltage Vo. This result is reasonable because this distortion stems from the body effect. Therefore, increasing Vo decreases the variation of the source-body voltage compared to its dc value caused by an input with fixed peak amplitude.2 Equation 5.56 also shows that the second-harmonic distortion is approximately proportional to 7, neglecting the effect of y on Vo- Similarly, third-harmonic...

17

Figure 5.35 Schematic of the top error amplifier and output transistor M Figure 5.35 Schematic of the top error amplifier and output transistor M Since Mi3 and Mu also form a current mirror, and since (W L) 4 (W L) 13, Substituting (5.131) and (5.132) into (5.133) gives , _ , (w l) 13 tail hie - 'bias + Since ID15 di6 when IDU )12, KSD14 VsDn (313 V gl Therefore, ignoring channel-length modulation, Substituting (5.130) into (5.136) and rearranging gives

18

Since the difference in the base-emitter voltages is proportional to the thermal voltage, comparing (4.266) with V0s 0 to (4.249) shows that the gain M here is proportional to (1 + R2 Ri). Rearranging (4.266) gives Vqut VeB2 + ( 1 + )(AV fi) + V05(out) Equations 4.267 and 4.268 show that the output contains an offset voltage that is a factor of (1 + R2fR'i) times bigger than the input-referred offset voltage. Therefore, the same gain that is applied to the difference in the base-emitter...

1ocoec2 5000e03 Socoe03 7000803 60ooeo3 5000e03 1000103 3cooe03 2 Oooe03 1000e03

1.OOOE-03 2.OC0E-03 3.OOOE-03 1.C0OE-O3 5.OOOE-03 .OOOE-03 1.0005-33 9.00 jE-03 .003E-33 1,000 s-32 5.508-01-' 5.ISE-01 i 5.138-01 ' 5.3U-01 -5.318-01 5.288-01 ' -5.218-01 < S.UI-01 ' 1.568-01 I -58E-01 1.728+00-' 2 288+00 2.308+00 2.318+30 < 2.32E+00 2.33E+00 ' 2.31E+00 + 2 -34E+00 2.318+00 i 35E+C0- OPERATING POINT INFORMATION TN0M NODE VOLTAGE NOES 'VOLTAGE 0 2 1.779E+00 0 3 1.OOOE-03 0 4 0 5 0. 0 6 1.727E+00 0 9 0 9 2.396E+00 0 100 2.500E+00 0 200 BIPOLAR JUSCTIOH TRANSISTORS SUBCKT...

2

Where (1.37) has been substituted for npo. Equation 1.48 shows that 3 . is maximized by minimizing the base width Wb and maximizing the ratio of emitter to base doping densities ND NA. Typical values of fir for npn transistors in integrated circuits are 50 to 500, whereas lateral pnp transistors (to be described in Chapter 2) have values 10 to 100. Finally, the emitter current is -(Ic + IB) - c + n) - F aF The value of aF can be expressed in terms of device parameters by substituting (1.48) in...

2 C

Taking the positive square root in the right-most formula in (9.70) yields a value that is larger than one. Adding this value to 1 gives a positive value for the term in parentheses subtracting this value from 1 gives a negative quantity with a smaller magnitude than the sum. Therefore, one zero is in the LHP and has a magnitude greater than gmi (2Cm2). The other zero is in the RHP and has a smaller magnitude than the LHP zero. As a result, the effect of the RHP zero is felt at a lower...

2 Cr

One disadvantage of the above method of compensation is that the value of C required is quite large (typically > 1000 pF) and cannot be realized on a monolithic chip. Many general-purpose op amps have unity-gain compensation included on the monolithic chip and require no further compensation from the user. (The sacrifice in bandwidth caused by this technique when using gain other than unity was described earlier.) In order to realize an internally compensated monolithic op amp, compensation...

20

And thus the collector-base resistance is r l0f30ro 10 X 100 X 20 kO 20 Mil The equivalent circuit with these parameter values is shown in Fig. 1.21. 1.4.8 Specification of Transistor Frequency Response The high-frequency gain of the transistor is controlled by the capacitive elements in the equivalent circuit of Fig. 1.20. The frequency capability of the transistor is most often specified in practice by determining the frequency where the magnitude of the short-circuit, common-emitter current...

20 40 6080100

Figure 2.29 Capacitance and depletion-layer width of an abrupt pn junction as a function of applied voltage and doping concentration on the lightly doped side of the junction11 where NB is the doping density in the epi material and VR is the reverse bias on the junction. The nomograph of Fig. 2.29 can also be used to determine the junction depletion-region width as a function of applied voltage, since this width is inversely proportional to the capacitance. The width in microns is given on the...

23 High Voltage Bipolar Integrated Circuit Fabrication

Integrated-circuit fabrication techniques have changed dramatically since the invention of the basic planar process. This change has been driven by developments in photolithography, processing techniques, and also the trend to reduce power-supply voltages in many systems. Developments in photolithography have reduced the minimum feature size attainable from tens of microns to the submicron level. The precise control allowed by ion implantation has resulted in this technique becoming the...

25

Circuit for Problem 12.23. V0i t Vod(t and Voc(t)l What are Vn(t Vi2 t Vid(t and Vlc(t)7 12.22 The op amp in Problem 12.4 is used with the CMFB scheme shown in Fig. 12.17. The circuit is perfectly balanced except that the CM-sense resistors are mismatched with the upper resistor Rcs 10.1 kil and the lower resistor Rcs2 9.9 kfL Assume the source followers and the CM-sense amplifier are ideal with gains of unity. (a) Compute the gains acms and adm-cms in (12.106). (b) Compute the...

2596211 5374e14 6601211 4146e14 1601211 6102e15

1.0002*07 1.1221*07 1.258E+07 1.4122*07 1.584E+07 1.7788*07 1. 958*07 2.2388*07 2.5118*07 2.8188*07 3.1628*07 3.5488*07 3.9818*07 4.4 6E 07 5.0118*07 5.6238*07 6.3098*07 7.079B*07 7.9438*07 8.9122+07 9.9998*07 1.1228*0 1.25B8*0I 1.4128*0 1.5848*0 1.7788*08 1.9958*08 2.2388*08 2.5118*08 2.8188*0 3.1628*0 3.5488*08 3.9811*08 4.4668*08 5.0111*08 5.6238*08 6.3098*08 7.0798*08 7.9438*08 8.9128*0 9.9998*0 1.1228*09 1.2588*09 1.4128*09 1.5848*09 1.7718*09 1.9958+09 2.2388*09 -7.928+01 -7.828*01...

27000

- 7.7391-01 0 1 1.3991+01 0 11 -1.2531+01 0 14 1.5001+01 0 3 7.7391-05 0 6 > 7.7391-01 0 9 1.3211+01 0 12 1.5001+01 - 0. -7.7391-05 1.3991+01 1.3991+01 bipolut jurcncm trahmstors 7.7391-01 1.5001+01 -1. 221+01 -1.5001+01 1. 151-02 1.0001+02 3.1271-02 2.6131+03 0. 0 Q2 0 H 9.(9(1-06 9.1911-04 7.7391-01 1.5001+01 -1.4221+01 -1.5001+01 1.(151-02 1.0001+02 3.1271-02 2.6131+03 0. 9.9971-06 9.9971-04 7.7421-01 1.3991+01 -1.3211+01 7.7391-05 1.3991-02 1.0001+02 3.1651-02 2.5871+03 0. 9.9971-06...

2x4x5

These values are marked on the root locus of Fig. 9.39. In this example, it is useful to compare the prediction of instability at Tq 13.2 with the results using the Nyquist criterion. The loop gain in the frequency domain is A series of trial substitutions shows that LT(jco) -180 for co 3.8 X 106 rad s. Note that this is close to the value of 4 X 106 rad s where the root locus was assumed to cross the jco axis. Substitution of a) 3.8X106 in (9. Ill) gives, for the loop gain at that frequency,

3

1.000E+05 1.2562+05 1.5B4E 05 1.9955*05 2.5115*05 3.1625+05 3-981E+05 5.0I1E-05 6.309E+05 7.9432+05 1.0005+06 1.253E+06 1.5812*05 1.9955+06 2.5115.06 3.162E+06 3.9B15-06 5.0115*06 6.309E*06 7 .9435+05 1.0005*07 1.2535+0 i.5845+07 1.9955+07 2.5115*0'' 3.1S25-C7 3.9815*07 5.0115*07 6.3095*0 7 9435*0 I. SBE+08 1.534E*08 1.9955*09 2.5115-09 3.1625+03 3.9915+09 5.0115+08 6.3095+08 7.5435*08 1.0005*09 1.775*02 .775+02 1.765*02 1.755*02 .745*02 1-73E.02 1.71E.02 1.635*02 1.575*02 1.635*02 1.595*02-1....

31

Since Vds3 Vd32, Vm y,32 Vtn, and (W L)3l (W L)32. This equation shows that Icm is dependent on the CM output voltage and independent of the differential output voltage because changes in the drain currents in M31 and M32 due to nonzero V* are equal in magnitude and opposite in sign. Therefore, these changes cancel when the drain currents are summed in (12.62). Applying KVL around the lower transistors A 30-M35 gives Vds3l Vds35 + Vgs33 - (12.63) Assuming that I0 33, we have Vgs30 V .33, and...

3160

This can be referred back to the input of the complete circuit of Fig. 11.38a in the standard manner. Consider the contribution to the equivalent input noise voltage. A voltage applied at the input of the full circuit of Fig. 11.38a gives Equating output noise current in (11.112) and (11.113), we obtain an equivalent input noise voltage due to i2oA as Thus the active load causes a contribution of 9.64 kil to the equivalent input noise resistance of the 741 op amp. The remaining important...

35 30 25 20 15 10 5

Figure 2.63 (a) Plan view and cross section of polysilicon resistor. resistor described in Section 2.6.2 and shown in Fig. 2.42. It displays large tolerance, high voltage coefficient, and high temperature coefficient relative to other types of resistors. Higher sheet resistance can be achieved by the addition of the pinching diffusion just as in the bipolar technology case. MOS Devices as Resistors. The MOS transistor biased in the triode region can be used in many circuits to perform the...

3600

Where the pole magnitudes are in radians per second. Equation 9.21 gives a unity-gain frequency where a(ja> ) 1 of 780 kHz. This is slightly below the design value of 1 MHz because the actual gain curve is 3 dB below the asymptote at the break frequency p . At 780 kHz the phase shift obtained from (9.21) is -139 instead of the desired -135 and this includes a contribution of -11 from pole p2. Although this result is close enough for most purposes, a phase margin of precisely 45 can be...

4

Figure 2.61 Typical variation of threshold voltage as a function of substrate bias for -channel devices with uniform channel doping (no channel implant) and with nonuniform channel doping resulting from threshold adjustment channel implant. Figure 2.61 Typical variation of threshold voltage as a function of substrate bias for -channel devices with uniform channel doping (no channel implant) and with nonuniform channel doping resulting from threshold adjustment channel implant. this value. The...

4242

Source degeneration is rarely used in MOS current mirrors because, in effect, MOS transistors are inherently controlled resistors. Thus, matching in MOS current mirrors is improved simply by increasing the gate areas of the transistors.2'3'4 Furthermore, the output resistance can be increased by increasing the channel length. To increase the output resistance while keeping the current and VGS - Vt constant, the W L ratio must be held constant. Therefore, the channel width must be increased as...

5

operato ponjr otor txoh TW*- 27.000 NO EC xVOLTAGI BODE a VOLTAGE BKS 0 3 4.7391-01 0 4 2.4981-02 0 5 +0 6 6.1271-02 0 100 > 1.0001+01 0 200 BIPOLAR JUNCTION TRANSISTORS SUBCAT 0 HPN 0 NPH 0 PNF IB 7.6931-07 1.2051-06 -5.9331-06 IC 1.923E-04 3.014E-04 -2.9661-04 VB 5.7101-01 5.3521-01 -5.3471-01 VCE 1.0691+00 1.0061+01 -9.9381+00 05.000 VOLTAGE -5.9601-01 '-1.0001+01 * OPERATOR POINT DffORHATICa THOU 27.000 BUS 'VOLTAGE BODE VOLTAGE BODE +0 3 4.1131-01 0 4 6.0371-02 0 5 +0 6 9.2591-02 0 100...

500

Using (9.139) in (9.137) shows that given these data, the maximum possible improvement in slew rate by use of emitter resistors is a factor of 21 times. Finally, in this description of methods of slew-rate improvement, we mention the class AB input stage described by Hearn.20 In this technique, the small-signal transconductance of the input stage is left essentially unchanged, but the limit Ixm on the maximum current available for charging the compensation capacitor is greatly increased. This...

500eos 500e05

-5.00E-05 . -5.00E-05 -5.00E-05 < -5.C0E-05-. -5.00E-05 -5.005-05 . -S.00E-05 < -5.00E-05 -5.00E-05 -5.CCE-05 -5.0CE-05 -5.005-05 . -S. OOE-05 < -5.005-05-' -5.005-05 . -5.005-05 . -5.00E-05 . -5.005-05 -5.0CE-05 . -5.0CE-C5 -5.C0E-05 . -5 005-05 . -5.005-05 Slightly So that a 1 the i-ranzisfors in the output branch of a current-mirror using -the circuit operate inthe active r ftion

6

As a < e 0, and the gain of the switched-capacitor amplifier approaches CXIC2 as predicted in (6.28). As a result, the circuit gain is said to be parasitic insensitive to an extent that depends on the op-amp gain. One important parameter of the switched-capacitor amplifier shown in Fig. 6.9a is the minimum clock period. This period is divided into two main parts, one for each clock phase. The duration of 02 must be long enough for the op-amp output to reach and stay within a given level of...

6 V

Figure 8.51 Circuit diagram of the 733 wideband monolithic amplifier. 8.20 A commercial wideband monolithic feedback amplifier (the 733) is shown in Fig. 8.51. This consists of a local series-feedback stage feeding a two-stage shunt-shunt feedback amplifier. The current output of the input stage acts as a current drive to the shunt-shunt output stage. (a) Assuming all device areas are equal, calculate the collector bias current in each device. (b) Calculate input impedance, output impedance,...

6210Operational Amplifier Equivalent Circuit

The effect of some of these deviations from ideality on the low-frequency performance of an op amp in a particular application can be calculated using the equivalent circuit shown in Fig. 6.14. (This model does not include the effects of finite PSRR or CMRR.) Here, the two current sources labeled bias represent the average value of dc current flowing into the input terminals. The polarity of these current sources shown in Fig. 6.14 applies for an npn transistor input stage. The current source...

625Common Mode Rejection Ratio CMRR

If an op amp has a differential input and a single-ended output, its small-signal output voltage can be described in terms of its differential and common-mode input voltages vid and vu) by the following equation where Adm is the differential-mode gain and Acm is the common-mode gain. As defined in (3.187), the common-mode rejection ratio of the op amp is From an applications standpoint, the CMRR can be regardedas_the_ hange in input offset voltage that results from a unit change in common-mode...

63 Basic Two Stage MOS Operational Amplifiers

Figure 6.15 shows a schematic of a basic two-stage CMOS op amp.4 5-6 A differential input ctdfTA nrttroc o f . 11------1 l______i ----o -- jti uiuwviiLiai input stage drives an active load followed by a second gain stage. An output stage is usually not - -------j wwv,. & clin -vu uutjjui suige is usuauy not used but may be added for driving heavy loads off-chip. This circuit configuration provides good common-mode range, output swing, voltage gain, and CMRR in a simple circuit that Figure...

633Input Offset Voltage

In Sections 3.5.6 and 6.2.3, the input offset voltage of a differential amplifier was defined as the differential input voltage for which the differential output voltage is zero. Because the op amp in Fig. 6.16 has a single-ended output, this definition must be modified here. Referring to the voltage between the output node and ground as the output voltage, the most straightforward modification is to define the input offset voltage of the op amp as the differential input voltage for which the...

638Layout Considerations

A basic objective in op-amp design is to minimize the mismatch between the two signal paths in the input differential pair so that common-mode input signals are rejected to the greatest possible extent. Mismatch affects the performance of the differential pair not only at dc, where it causes nonzero offset voltage, but also at high frequencies where it reduces the common-mode and power-supply rejection ratios. Figure 6.22a shows a possible layout of a differential pair. Five nodes are labeled...

66 MOS Folded Cascode Operational Amplifiers

Figure 6.26 shows two cascode circuits where VDD 0 for simplicity. In Fig. 6.26a, both Mi and Mm are p-channe devices. In Fig. 6.26b, M is still a p-channel device but M A Figure 6.26 shows two cascode circuits where VDD 0 for simplicity. In Fig. 6.26a, both Mi and Mm are p-channe devices. In Fig. 6.26b, M is still a p-channel device but M A Figure 6.26 (a) Standard cascode configuration. (b) Folded-cascode configuration. is now an -channel device. In both cases, however, M is connected in a...

67 MOS Active Cascode Operational Amplifiers

One way to increase the gain of the folded-cascode op amp without cascading additional stages is to add another layer of cascodes. See Problem 6.21. Although this approach gives a gain on the order of (gmr0)3, it reduces the output swing by at least another overdrive in each direction. This reduction becomes increasingly important as the difference between the power-supply voltages is reduced in scaled technologies. To increase the op-amp gain without reducing the output swing, the...

681 The dc Analysis of the 741 Operational Amplifier

The first step in evaluating the performance of the circuit is to determine the quiescent operating current and voltage of each of the transistors in the circuit. This dc analysis presents a special problem in op-amp circuits because of the very high gain involved. If we were to begin the dc analysis with the assumption that the two input terminals are grounded and then try to predict the output voltage, we would find that a small variation in the beta or output resistance of the devices in the...

682 Small Signal Analysis of the 741 Operational Amplifier

Our next objective is to determine the small-signal properties of the amplifier. We will break the circuit up into its three stages the input stage, gain stage, and output stage and determine the input resistance, output resistance, and transconductance of each stage. Consider first the ac schematic of the input stage as shown in Fig. 6.37. Here we have assumed a pure differential-mode input to the circuit we will consider common-mode inputs later. As a result, the collectors of Q and < 22 as...

691 Design of Low Drift Operational Amplifiers

The offset voltage of multistage differential amplifiers depends primarily on the offset of the first stage, provided that the stage has sufficiently high voltage gain. Thus the design of low-offset amplifiers is primarily a problem of designing an input stage in which as few component pairs as possible contribute to the stage offset voltage. In the 741, the input stage is relatively complicated since it provides gain, level shifting, and differential-to-single-ended conversion. A more optimum...

692 Design of Low InputCurrent Operational Amplifiers

In instrumentation applications in which the signal source has a low internal impedance, the input offset voltage and its associated drift usually place a lower limit on the dc voltage than can be resolved. When the source impedance is high, however, the input bias current and input offset current of the op amp flowing in the source resistance or the gain-setting resistors can be important in limiting the ability of the circuit to resolve small dc signals. Furthermore, many applications involve...

7143e01 7291e05 8810e06 9318e06 1470e06 3794e06 3921106 4792e06 1316e05

1.000E+00 1.021E-04 1.233E-05 1.304E-05 2.058E-06 5.312E-06 5.489E-06 6.708E-06 1.842E-05 1.764E+02 8.825E+01 9.282E+01 8.5612+01 1.0241+02 7.440E+01 4.849E+00 9.9021+01 1.7471+02 -8.8141+01 -8.357E+01 -2.620E+02 -2.788E+02 -1.0201+02 -1.7151+02 -7.7381+01 -3.5111+02 TOTAL HARMOanC DISTORTIOH 1.058E-02 FERCEHT FOURIER COMPOHEHTS OF TRAHSIZHT RESPONSE V(9,10) DC COKPOHEHT - 1.793D+00 HARMCNIC FREQUEHCT FOURIER NORMALIZED PHASE NORMALIZED HO (HZ) COSIPOBttHT COKFCNEHT (DEG) PHASE (DEG)

72 Single Stage Amplifiers

The basic topology of the small-signal equivalent circuits of bipolar and MOS single-stage amplifiers are similar. Therefore in the following sections, the frequency-response analysis for each type of single-stage circuit is initially carried out using a general small-signal model that applies to both types of transistors, and the general results are then applied to each type of transistor. The general small-signal transistor model is shown in Fig. 7.1. Table 7.1 lists the parameters of this...

783

Common centroid geometry, 440-442, 476,477 configuration, 202 Common-collector-common-emitter configuration, 202 Common-collector configuration, 191, 503 Common-drain configuration, 195, 509, 591 Common-emitter-common-base configuration, see Cascode configuration Common-emitter configuration, 175, 490, 494 Common-emitter frequency response, 490, 494 Common-emitter output stage, 576 Common-gate configuration, 186, 188, 190.515, 525 Common-gate frequency response, 515 Common-mode feedback, 228,...

7t

Where Rc is the collector resistor in the Gilbert multiplier and gm is the transconduc-tance of the transistors. The phase detector output voltage then becomes proportional to the amplitude V, of the incoming signal, and if the signal amplitude varies, then the loop gain of the phase-locked loop changes. Thus when the signal amplitude varies, it is often necessary to precede the phase detector with an amplifier limiter to avoid this problem. In FM demodulators, for example, any amplitude...

81 Ideal Feedback Equation

Consider the idealized feedback configuration of Fig. 8.1. In this figure 5, and SQ are input and output signals that may be voltages or currents. The feedback network (which is usually linear and passive) has a transfer function and feeds back a signal Sfb to the input. At the input, signal Sfb is subtracted from input signal at the input differencing node. Error signal Se is the difference between St and Sfb, and S is fed to the basic amplifier with transfer function a. Note that another...

841 Series Shunt Feedback

Suppose it is required to design a feedback amplifier that stabilizes a voltage transfer function. That is, a given input voltage should produce a well-defined proportional output voltage. This will require sampling the output voltage and feeding back a proportional voltage for comparison with the incoming voltage. This situation is shown schematically in Fig. 8.4. The basic amplifier has gain a, and the feedback network is a two-port with transfer function that shunts the output of the basic...

843 Shunt Series Feedback

The shunt-series configuration is shown in Fig. 8.11. The feedback network samples ia and feeds back a proportional current ifb fiD. Since the desired output signal is a current i0, it is more convenient to represent the output of the basic amplifier with a Norton equivalent. In this case both a and are dimensionless current ratios, and the ideal input source is a 8,5 Practical Configurations and the Effect of Loading 563 Basic amplifier 8,5 Practical Configurations and the Effect of Loading...

851 Shunt Shunt Feedback

Consider the shunt-shunt feedback amplifier of Fig. 8.9. The effect of nonideal networks may be included as shown in Fig. 8.13a, where finite input and output admittances are assumed in both forward and feedback paths, as well as reverse transmission in each. Finite source and load admittances ys and yL are assumed. The most convenient two-port Figure 8.13 (a) Shunt-shunt feedback configuration using the y-parameter representation, (b) Circuit of (a) redrawn with generators _y2i v,- and y 2av0...

852 Series Series Feedback

Consider the series-series feedback connection of Fig. 8.12. The effect of nonideal networks can be calculated using the representation of Fig. 8.16 . In this case the most convenient two-port representation is the use of the open-circuit impedance parameters or z parameters because the basic amplifier and the feedback network are now connected in series at input and output and thus have identical currents at their terminals. As shown in Fig. 8.17, the z parameters specify the network by...

853 Series Shunt Feedback

Series-shunt feedback is shown schematically in Fig. 8.4. The basic amplifier and the feedback network have the same input current and the same output voltage. A two-port representation that uses input current and output voltage as the independent variables is the hybrid -parameter representation shown in Fig. 8.22. The h parameters can be used to represent nonideal circuits in a series-shunt feedback as shown in Fig. 8.23a. Summation of voltages at the input of this figure gives Vs (zs + hUa +...

854 Shunt Series Feedback

Shunt-series feedback is shown schematically in Fig. 8.11. In this case the basic amplifier and the feedback network have common input voltages and output currents, and hybrid g parameters as defined in Fig. 8.29 are best suited for use in this case. The feedback circuit is shown in Fig. 8.30a, and, at the input, we find that (ys + glla + gllf)Vi + (gl 2 + g 12 f)io node, and the feedback function can be identified as The gain a of the basic amplifier is determined by calculating the current...

88 Feedback Circuit Analysis Using Return Ratio

The feedback analysis presented so far has used two-ports to manipulate a feedback circuit into unilateral forward amplifier and feedback networks. Since real feedback circuits have bilateral feedback networks and possibly bilateral amplifiers, some work is required to find the amplifier a and feedback networks. The correct input and output variables and the type of feedback must be identified, and the correct two-port representation (y, z, h, or g) must be used. After this work, the...

882 Closed Loop Impedance Formula Using Return Ratio

Feedback affects the input and output impedance of a circuit. In this section, a useful expression for the impedance at any port in a feedback circuit in terms of return ratio9 is derived. Consider the feedback circuit shown in Fig. 8.44. This feedback amplifier consists of linear elements passive components, controlled sources, and transistor small-signal models. A controlled source k that is part of the small-signal model of an active device is shown explicitly. The derivation is carried out...

883 Summary ReturnRatio Analysis

Return-ratio analysis is an alternative approach to feedback circuit analysis that does not use two-ports. The loop transmission is measured by the return ratio Sft. The return ratio is a different measure of loop transmission than af from two-port analysis. (The return ratio is referred to as loop gain in some textbooks. That name is not associated with 91 here to avoid confusion with T af, which is called loop gain in this chapter.) For negative feedback circuits, 2ft > 0. In an ideal...

89 Modeling Input and Output Ports in Feedback Circuits

Throughout this chapter, the source and load impedances have been included when analyzing a feedback circuit. For instance, the inverting voltage-gain circuit in Fig. 8.47a, with source resistance Rs and load resistance RL, can be analyzed using the two-port or return-ratio methods described in this chapter. The resulting model is shown in Fig. 8.47 . The source and load resistances do not appear explicitly in the model, but the gain A, input resistance Rh and output resistance R are functions...

91

The return ratio can be used to check stability of an amplifier with a single feedback loop because A f_ and d are stable transfer functions associated with passive networks, and Ms) is stable because it is the signal transfer around a loop that consists of one gain stage or a cascade of stable gain stages. Therefore the zeros of 1 + 2ft(s), which are poles of the closed-loop gain A, determine the stability of the feedback circuit.24 From the Nyquist stability criterion, these zeros are in the...

92Relation Between Gain and Bandwidth in Feedback Amplifiers

Chapter 8 showed that the performance improvements produced by negative feedback were obtained at the expense of a reduction in gain by a factor (1 + T), where T is the loop gain. The performance specifications that were improved were also changed by the factor (1 + T). In addition to the foregoing effects, negative feedback also tends to broadband the amplifier. Consider first a feedback circuit as shown in Fig. 9.1 with a simple basic amplifier whose gain function contains a single pole...

941 Theory of Compensation

Consider again the amplifier whose gain and phase is shown in Fig. 9.8. For the feedback circuit in which this was assumed to be connected, the forward gain was A0, as shown in Fig. 9.8, and the phase margin was positive. Thus the circuit was stable. It is apparent, however, that if the amount of feedback is increased by making larger (and thus A0 smaller), oscillation will eventually occur. This is shown in Fig. 9.11, where fi is chosen to give a zero phase margin and the corresponding overall...

942 Methods of Compensation

In order to compensate a circuit by the common method of narrowbanding described above, it is necessary to add capacitance to create a dominant pole with the desired magnitude. One method of achieving this is shown in Fig. 9.16, which is a schematic of the first two stages of a simple amplifier. A large capacitor C is connected between the collectors of the input stage. The output stage, which is assumed relatively broadband, is not shown. Figure 9.15 Gain and phase versus frequency for an...

943 Two Stage MOS Amplifier Compensation

The basic two-stage CMOS op amp topology shown in Fig. 6.16 is essentially identical to its bipolar counterpart. As a consequence, the equivalent circuit of Fig. 9.21 can be used to represent the second stage with its compensation capacitance. The poles of the circuit are again given by (9.32) and (9.33) and the zero by (9.27a). In the case of the MOS transistor, however, the value of gm is typically an order of magnitude lower than for a bipolar transistor, and the break frequency caused by...

944 Compensation of Single Stage CMOS Op Amps

Single-stage op amps, such as the telescopic cascode or folded cascode, have only one gain stage therefore Miller compensation is not possible. These op amps have high open-loop output resistance and are typically used in switched-capacitor circuits, where the load is purely capacitive. Therefore, the dominant pole is associated with the output node, and the load capacitor provides the compensation. A simplified, fully differential, telescopic-cascode op amp is shown in Fig. 9.30 . The...

945 Nested Miller Compensation

Many feedback circuits require an op amp with a high voltage gain. While cascoding is commonly used to increase the gain in op amps with a total supply voltage of 5 V or more, cascoding becomes increasingly difficult as the power-supply voltage is reduced. (See Chapter 4.) To overcome this problem, simple gain stages without cascoding can be cascaded to achieve high gain. When three or more voltage-gain stages must be cascaded to achieve the desired gain, the op amp will have three or more...

951 Root Locus for a Three Pole Transfer Function

Consider an amplifier whose transfer function has three identical poles. The transfer function can be written as where aQ is the low-frequency gain and p is the pole magnitude. Consider this amplifier placed in a negative-feedback loop as in Fig. 9.1, where the feedback network has a transfer function , which is a constant. If we assume that the effects of feedback loading are small, the overall gain with feedback is hi gmoRog,nlRigm2R2 20,000 86 dB Figure 9.35 Root locus for a feedback...

953 Root Locus for Dominant Pole Compensation

Consider an op amp that has been compensated by creation of a dominant pole at Pl. If we assume the second most dominant pole is at p2 and neglect the effect of higher order poles, the root locus when resistive feedback is applied is as shown in Fig. 9.40. Using rules 1 and 2 indicates that the root locus exists on the axis between Pl and p2, and the breakaway point is readily shown to be using rule 6. Using rules 7 and 8 shows that the asymptotes are at 90 to the real axis and meet the axis at...

954 Root Locus for Feedback Zero Compensation

The techniques of compensation described earlier in this chapter involved modification of the basic amplifier only. This is the universal method used with op amps that must be compensated for use with a wide variety of feedback networks chosen by the user. However, this method is quite wasteful of bandwidth, as was apparent in the calculations. In this section, a different method of compensation will be described that involves modification of the feedback path and is generally limited to...

96 Slew Rate

The previous sections of this chapter have been concerned with the small-signal behavior of feedback amplifiers at high frequencies. However, the behavior of feedback circuits with large input signals (either step inputs or sinusoidal signals) is also of interest, and the effect of frequency compensation on the large-signal, high-frequency performance of feedback amplifiers is now considered. t Figure 9.48 Circuit for testing slew-rate performance. and f0 is the -3-dB frequency. Since the...

962 Methods of Improving Slew Rate in Two Stage Op Amps

In order to examine methods of slew-rate improvement, a more general analysis is required. This can be performed using the circuit of Fig. 9.52, which is a general representation of an op amp circuit. The input stage has a small-signal transconductance gmI and, with a large input voltage, can deliver a maximum current Ixm to the next stage. The compensation is shown as the Miller effect using the capacitor C, since this representation describes most two-stage integrated-circuit op amps. From...

965 Effect of Slew Rate Limitations on Large Signal Sinusoidal Performance

The slew-rate limitations described above can also affect the performance of the circuit when handling large sinusoidal signals at higher frequencies. Consider the circuit of Fig. 9.48 with a large sinusoidal signal applied as shown in Fig. 9.57a. Since the circuit is connected as a voltage follower, the output voltage V0 will be forced to follow the V, waveform. The maximum value of dVJdt occurs as the waveform crosses the axis, and if V, is given by As long as the value of dVi dt max given by...

Vod I Voc VcMWod

4 4 V23 - (Vod 2)2 ) 8 4V2v23 - (Vod 2)2 If Vod 21 < 2Vov23 , this equation reduces to (12.56). To interpret (12.61), first consider the case when Voc VCM. Then (12.61) shows that the CM-sense output current is constant with Icms 20. Whereas Icms is constant, (12.59) and (12.60) show that Id22 and Im are not constant if Vod is nonzero and time-varying, and Id22 and Id23 are nonlinear functions of Vod (see the plot in Fig. 3.51). However, the variation in Id22 due to nonzero V0d is equal and...

A412

Matched current sources are often required in MOS analog integrated circuits. The factors affecting this mismatch can be calculated using the circuit of Fig. 4.52. The two transistors Mi and M2 will have mismatches in their W L ratios and threshold voltages. The drain Figure 4.53 Current mirror with two outputs used to compare voltage- and current-routing techniques. circuit with desirable properties. For example, a self-biased band-gap reference might be used to make fa insensitive to changes...