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Main Board Interface (sheet 4)

PAL mode

The OSD chip is natively PAL-capable. Selecting PAL mode involves both programming internal OSD registers and selecting the 4xfsc crystal with U12-4. The OSD generates the 625-line/50Hz PAL raster and encoded PAL color.

SECAM considerations

For SECAM compatibility, the fullscreen OSD is configured for 50Hz monochrome grayscale. During overlay, switch U8-15 bypasses the high-frequency SECAM color-subcarriers around the OSD. With SECAM, overlaid characters are not "carved out" of the thru video as well as they are in PAL or NTSC; the color of the thru-video bleeds through the overlay.

OSD Serial Control

A command to the OSD chip consists of two 8-bit transfers, LSB first. Individual bits are clocked in on the rising edge of the SER_CTRL_CLK/ while the chip is selected by OSD_CS/.

Control Registers

Two 8-bit 74HC595 shift registers U14,U15 are cascaded to form one logical 16-bit register. Bits are clocked into the input shift registers on the rising edge of SER_CTRL_CLK/ in a single 16-bit transfer. The output parallel registers are updated on the rising edge of the 'chip select' VIDEO_REG_CS/, which is simply a clockto the output registers. The shift registers are cleared by RESET/, during which time the output registers are repeatedly loaded by 15kHz taken from the sync detect AFC. Clearing the register results in a proper reset state for all bits except the enable to the record Y multiplexer U5. U2-14 is used as an inverter to give RYEN the proper sense, and so U5 is disabled during reset.

Control Bit Assignments

D0:2

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