Xpander Circuitry Overview

The key to the outstanding performance and features of the Xpander is the intensive use made of its two built-in microprocessors. The first microprocessor is called the main processor and is located on the processor board. Its main tasks are :

— Collecting and processing information coming from the front panel controllers ( encoders and switches ).

— Collecting and processing information coming from the outside of the Xpander through MIDI or control input jacks ( CVs and GATES, PEDAL etc.).

— Controlling the displays ( alpha numeric and LEDs ).

— Storing sound parameters in battery back up memory.

— Receiving and sending cassette data.

— Controlling the sound parameters of the voices.

The second microprocessor, called the voice processor, is located on the voice printed circuit board. The voice processor receives the sound parameter data from the main processor ( VCO frequency, LFO 2 speed, envelope 3 attack time etc..) and generates all the modulations and controls that drive the analog circuitry. It also performs a number of automatic calibrations and corrections which insure the accurate behavior of the analog circuitry of each voice.

The Xpander's circuitry is spread on five printed circuit boards.

— The processor board

— The display board

— The power supply board

THE PROCESSOR BOARD:

The processor board is located in the upper right corner ( when the unit is open ). It holds : -The 16 MHZ clock. —The main processor.

—The power up/down detection circuit (PUP).

—The battery back up memory for the program retention as well as the battery itself. —The MIDI in and out circuitry. —The cassette in and out circuitry. —Some of the LED latches. --The analog noise generator

THE POT BOARD:

The pot board is located in the upper left. It holds: —The switch decoding circuit —The external CVs and gates circuit. --The pedal circuit. --The step encoder decoding circuit. —Some of the LED latches. --The audio master volume control.

THE DISPLAY BOARD:

The display board is located on top of the pot board. It holds: —The decoding for the display's digits. —The high voltage buffer for the diplays. —The three 40-digit vacuum fluorescent display tubes.

THE VOICE BOARD:

The voice board is located on the bottom left. It holds: —The processor interface circuit. —The voice processor and its ROM and RAM. —The DAC

--The analog circuitry for the 6 voices. —The panning circuit.

THE POWER SUPPLY:

The power supply is located on the bottom right.

The following chapter provides information only on the parts of the Xpander's circuitry which present some originality and innovation. A basic knowledge of synthesizer electronic circuits is required.

SWITCHING POWER SUPPLY:

In order to decrease the heat dissipation without using bulky heat sinks, the Xpander uses a switching power supply which operates as follows: The line AC voltage is first stepped down, rectified and filtered by Tl, 01, 02 and C3 to produce a low DC voltage (approximately 13 volts). This DC voltage is then chopped (switched) by Q1 at a frequency of approximately 30 KHz to produce a-variable pulse width wave. This pulse is applied through the primary of the step transformer T2 which provides in return on its secondary windings all the different voltages used in the Xpander. Those AC voltages (30 KHz frequency) are then rectified (D5,D4,D6,D7), filtered (C7,C5,C8,C9,C1,C10) and if necessary, regulated (U2,U1,U3). Finally, the 5 volt supply is fed back into the "oscillator/pulse width modulator" integrated circuit U4 to modulate the pulse width and provide the basic voltage regulation.

The advantage of this method over the conventional voltage regulation scheme lies in the fact that the regulation is achieved by modulating the width of a pulse wave rather then the resistance of a transistor. The modulated pulse turns on and off the power MOS transistor Ql which will therefore always be in one of the two following states: ON: voltage across =0 , drain current = max — > power=0 OFF: voltage across =max , drain current = 0 —> power=0 As there is no power across the transistor in both states, there is no heat production.

The Internal Parts Tlp411u Names

DUAL MICROPROCESSOR INTERFACE:

The two microprocessors of the Xpander are running two different programs in parallel; the main processor is mainly in charge of collecting and processing the information of the front panel, and the voice processor generates the envelopes, LFOs, LAG etc. for the 6 voices. At some point it is necessary for the main processor to write a new sound parameter into the voice processor memory (for example, a new speed value for an LFO or a new note value for a voice). This is done through the microprocessor interface circuitry located on the voice hoard. This circuitry includes: one bidirectional octal buffer (U904), four 3-state buffers (U903, U902, U90I, U916), 3 OR gates (U906) and a transistor (Q901).

Every time the main processor has to change a parameter in the voice processor memory, the following sequence of events occurs:

A) The main processor sets the HALTREQ* (halt request) line LOW (pin 10 of U906 OR gate).

8) If the voice processor did not previously set the HALTDS (halt disabled) line high, the voice processor will halt, meaning that it will:

1) Stop execution of its program after completion of the current instruction.

2) Put its data and address lines in high impedance state.

3) Set high the BA line (bus available).

C) BA high will do two things:

1) Through U904,U903,U902,U90t it will connect the data and address lines of the main processor to the data and address line of the voice processor and through U903 and U916 it will switch the read and write lines of the voice processor for the read and write lines of the main processor.

2) Set the HALTAKN* (halt aknowledge) line low (Q901 collector).

D) By sensing the HALTAKN* line low, the main processor knows that its data and address lines are now connected to the voice processor memory and that it can therefore read from or write into it.

E) When the data transfer is completed, the main processor sets the HALTREQ* line high again, allowing the voice processor to retrieve control of its bus and resume its operation.

NOTE: If during normal operation (no tuning or cassette transfer) the voice processor does not aknowledge a halt request in less than 1 second, the main processor will sense a malfunction and will display: "VOICE PROCESSOR MALFUNCTION".

Oberheim Xpander Battery

STEP ENCODERS:

In order to facilitate parameter edition, the Xpander uses six step encoders located at the bottom of the PAGE MODIFIER section.

Step encoders, from the outside, seem to behave and look like 360 degree potentiometers, but in practice operate in a completely different way.

They are internally made of two switches and a toothed wheel with 30 teeth. Each of the steps (clicks) generates a sequence of closing and opening for the two switches si and s2. The sequence will be different according to the direction of the rotation.

Each encoder is connected to decoding circuitry that automatically senses every step and its direction.

Consider the circuitry of the encoder number I where R22, R21, C3 and C4 debounce the encoder switches. Whenever one of the 2 switches closes, pin 10 of the NOR gate U10 will go low until both switches are open again. This low to high transition will latch a high level on pin 9 of U8 indicating that the sequence of events for one step has been completed. The main processor can read the status of the six encoders through the tri-state gate U9. In parallel, pin 5 of U8 is set high or low according to the direction of the rotation of the encoder. The main processor can read the direction through the tri-state gate U5. Note that when U5 is enabled (DIR* is low) all the step sensor latches are reset.

Point Dual Fluorescent Display

VACUUM FLUORESCENT DISPLAYS:

The three 40-digit vacuum fluorescent displays (VFD) and their drivers are located on the display board.

The VFD consists of three basic electrodes in an evacuated glass chamber (see fig. below). The electrodes are the cathode, grid and anode. The cathode is a small diameter oxide-coated tungsten filament running across the length of the display and is directly heated by an AC current. The grid is a thin metal screen mesh covering the area over each digit. The anode is coated with phosphor and is arranged in 16 independent segments for each digit.

Grid mesh Filament (cathode)

PerflgHP-y ^ ^-phosphor coaled anode (16 per digit)

Glass chamber

When a positive voltage is applied to the grid 8nd enode, the resultant electrical field will accelerate electrons toward the grid. Since the grid is a mesh, most of the electrons will pass through the grid. Electrons that have passed the grid are further accelerated toward the anode, but collide with the phosphor before reaching it. The electrons deposit most of their energy on the phosphor. This transfer of energy excites the phosphor, which emits a rich blue-green light.

All the identical segments of the 40 digits are connected together and brought out on pins ANO through AN 15 (for example, all the underline segments are connected to pin ANO). The 40 grids are individusly available on pin Gl through G40.

The VFD drive circuitry is shown on the next page. On the left side are the grid drivers (UII,9,1,2,5,6,7,8,13,14,17,18), and on the right side are the anode drivers (U 12,3,4,21,22,23,24,25,26,15,16,19,20). Under the control of the main processor, the grids of the 3 VFD are sequentially turned on one at a time from Gl through G40. Before turning on the next grid, a new combination of anodes, determining the displayed pattern, is latched for each of the 3 VFDs.

Roland Jx8p Vfd Display

GATE AND CV INPUTS:

The six gates, chain advance and trigger signals are buffered through Q1 and the seven transistors contained in U22. The eight resistors R57 through R63 are either pulling up or down the input according to the state of the lines PULL 1 through PULL7. These lines will be set low if the corresponding gate polarity is set for + and set high if the gate polarity is set for - . This setup automatically forces an unused input into its passive state.

The CV and pedal voltages present on the rear panel jacks are multiplexed through U17 under the control of the main processor. Each of the voltages are then sequentially converted to an 8-bit digital value by the analog to digital converter U20. Only the six most significant bits are used. The diodes 055 through D71 limit the range of the input voltage to 0 and 5.6 volts.

Project Multiplexer Ceronix

VCO TEMPERATURE COMPENSATION:

Each 3374 dual VCO chip used on the analog voices includes a temperature sensor circuit that provides on pin 10 a voltage proportional to the chip internal temperature. These voltages are filtered and buffered on each voice by CX35 and UX05. The six voltages are then routed to U805 in the DAC area. The circuitry composed of U805, U614, UR15 allows selection, under the control of the m8in processor, of one of the six temperature reference voltages or a fixed reference to be the DAC. reference Because the DAC used in the Xpander is a multiplying DAC, the voltage on the output of the DAC circuitry is directly proportional to the reference. When the DAC loads a sample arid hold controlling the frequency of a VCO, the temperature reference voltage of this VCO will be used as reference for the DAC. Therefore , if the internal temperature of 8 VCO rises, its frequency voltage control will raise proportionally, keeping the resulting frequency stable. When the DAC loads the sample and hold of a non-temperature dependant parameter (Pulse width for example) the fixed voltage reference will be used as DAC reference.

The temperature stability of the VCO's frequency resulting from this method is far better than the one achieved with the CEM 3340 VCO chip because the correction scaling is performed by the multiplying DAC rather than by the analog multiplier built into the CEh 3340.

Vfd Driver

HIGH RESOLUTION DAC:

The Xpander uses a 14 bit DAC which provides the high resolution needed for the generation of smooth and accurate modulations However an even higher resolution is required to achieve the very high standard of tuning accuracy that Oberheim likes to offer. This is accomplished by the circuitry on the right of the DAC U811 (see next page ).

Whenever a control voltage requiring a very high level of resolution (VCO or VCF frequency control) must be generated, this voltage will be obtained in two phases:

1) The DAC is first loaded with the fine tune value which is stored in the sample and hold formed by U814, C805 and U815

2) The previously mentioned sample and hold's input is then disconnected from the DAC and the DAC is loaded with the most significant part of the control value. At this moment U8I4 connects the output of U815 (pin 14) to the summing node of U8I3 making its output equal to the sum of the control value and the fine tune value previously stored in C805. Simultaneously, the final destination sample and hold is connected to US 13 output and stores the final value.

As the summing resistor for the fine tune sample and hold is three times the value of the other summing resistors (R849 and R846), the resolution obtained from the fine tune sample and hold is three times better than the original resolution of the 14 bit DAC.

When a control voitage which does not require this extra resolution has to be loaded in a sample and hold, the connection between pin 14 and 12 of U814 is open and the S&H is loaded in one phase.

Note that when the very high resolution mode is used, R850 is connected to the summing node of U8I3 bringing its output down of approximately 5 volts. This allows the use of a -5 to +5 voltage range for the VCO and VCF frequency controls, making the line noise proportionally smaller.

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