0100 E3
2117 H10 2118G11 2119G12 2120G12 7103 B3 7104-1 D1 7104-2 D2 7104-3 C3 7104-4 C4 7104-5 D3 7104-6 D4 7107 H13 F100 B2 F101 B6 F103 E3 F104 E3 F105 E3 F106 F3 F107 F3 F110 H3 F111 H3 F112 B9 F114 H5 F115 E8 F116 E13 F117 E13 F118 E13 F119 E13 F120 E13 F121 F13 F122 F13 F123 F13 F124 F13 F125 F13 F126 F13 F127 F13 F128 F13 F129 H12 F130 E10 F131 E9 F132 F10 F133 F11 F134 F9
11
127V 37 110V - 240V 55 220V - 240V 75 97 25 W (typical) < 3 W Test equipment Fluke 54200 TV Signal generator Test streams Philips Standard test pattern Frequency range Gain (ANT IN - ANT OUT) Radio Interference max. input voltage, at 750, 3 tone method (< -40dB) Video Modulation Frequency response Audio Modulation 1kHz tone 80 15 0 3dB, 0 4.2MH 12kHz, tol. 4kHz PLL tuning with AFC for optimum reception Frequency range Sensitivity at 40 dB S N Channel 25 503,25 MHz, Test pattern standard...
141
Superimposed DC-level on pin 4 (load > 100k0) < 2.4V is detected as 4 3 aspect ratio > 3.5V is detected as 16 9 aspect ratio Input voltage Y Input impedance Y Input voltage C Input impedance C Video Cinch Input voltage Input impedance 1.4.2 Audio Video Front Input Connectors Superimposed DC-level on pin 4 (load > 100 kO) < 2.4V is detected as 4 3 aspect ratio > 3.5V is detected as 16 9 aspect ratio Input voltage Y Input impedance Y Input voltage C Input impedance C Component Video...
35762 G2 35763 G2 35764 G2
3578 G2 3579-1 H2 3579-2 H2 3579-3 H2 3579-4 H2 3583 H2 3584-1 H2 3584-2 I2 3584-3 I2 3584-4 I2 3695 F6 4523 C4 4581 H2 5511 D2 5518 B2 5521 C2 5525 C6 6506 C6 6521 D6 6595 F6 7501 H6 7515 A2 7521 C4 7595 F5 T501 C1 T502 C1 T503 C1 T504 C1 T505 C1 T506 C1 T507 D1 T508 D1 T509 D1 T510 D1 T511 D1 T515 A2 T516 C6 T517 F6 T518 A8 T519 A8 T520 A8 T521 A8 T522 B8 T523 B8 T524 B8 T525 B8 T526 B8 T527 B8 T528 B8 T529 C8 T530 C8 T531 C8 T532 C8 T533 C8 T534 C8 T535 C8 T536 A13 T537 A13 T538 A13 T539 A13...
Class 1 Laser Product
CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM ADVARSEL SYNLIG OG USYNLIG LASERSTR LING VED BNING UNDG UDS TTELSE FOR STR LING ADVARSEL SYNLIG OG USYNLIG LASERSTR LING N R DEKSEL PNES UNNG EKSPONERING FOR STR LEN VARNING SYNLIG OCH OSYNLIG LASERSTR LNING N R DENNA DEL R PPNAD BETRAKTA EJ STR LEN Note Use of controls or adjustments or performance of procedure other than those specified herein, may result in hazardous radiation exposure. Avoid direct exposure to...
I
Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus holder isolation is implemented, the ISO terminal should be tied high to disable the differentiation logic. For additional...
1
This terminal monitors the active power status of the link layer controller and controls the state of the PHY-LLC interface. This terminal should be connected through a 10-k resistor either to the Vdd supplying the LLC, or to a pulsed output which is active when the LLC is powered (see Figure 9). A pulsed signal should be used when an isolation barrier exists between the LLC and PHY. (See Figure 10.) The LPS input is considered inactive if it is sampled low by the PHY...
Bcu
Asserting this terminal low resets the internal logic. An internal pullup resistor to Vdd is provided so only an external delay capacitor is required for proper power-up operation (see power-up reset in the Application Information section). The RESET terminal also incorporates an internal pulldown which is activated when the PD input is asserted high. This input is otherwise a standard logic input, and may also be driven by an open-drain type driver
Pmy
A high on this terminal turns off all internal circuitry except the cable-active monitor circuits, which control the CNA output (64-terminal PAP package only). Asserting the PD input high also activates an internal pulldown on the RESET terminal to force a reset of the internal control logic. (PD is provided for legacy compatibility and is not recommended for power management in place of IEEE 1394a-2000 suspend resume LPS and C LKON features.)
Ind Fxd Lhl08 S 2u2 Pm20 A
TRANSFORMER 6RG (SAGA) B 37 only TFM SIG RF 049S20056 B 55, 75, 97 only 6101 4822 130 30621 1N4 1 48 55 only 6200 9322 129 41685 BZM55-C12 6201 9322 129 41685 BZM55-C12 6202 9322 129 41685 BZM55-C12 6203 9322 129 41685 BZM55-C12 6204 9322 129 41685 BZM55-C12 6205 9322 129 41685 BZM55-C12 6206 9322 129 41685 BZM55-C12 6210 9322 129 41685 BZM55-C12 6211 9322 129 41685 BZM55-C12 6212 9322 129 41685 BZM55-C12 6213 9322 129 41685 BZM55-C12 6214 9322 129 41685 BZM55-C12 6215 9322 129 41685 BZM55-C12...
Info
Satellite signa Cable satellite box jack panel satellite signa Cable satellite box jack panel 2a Connect existing antenna cable satellite signal (or from the Cable Satellite Box RF OUT or TO TV ) to the ANTENNA S- input jack at the back of the DVD recorder. 2b Use the supplied RF coaxial cable to connect the DVD recorder's TV output jack to your TV's antenna input jack. 2c Use the supplied AV cables (yellow red white ends) to connect the DVD recorder's VIDEO (CVBS) and AUDIO L R OUT2 jacks to...
Snr
Output voltage 2 channel mode Channel unbalance (1kHz) Crosstalk 1kHz Crosstalk 20Hz-20kHz Frequency response 20Hz-20kHz Signal to noise ratio (A-weighted) Dynamic range 1kHz Distortion and noise 1kHz Distortion and noise 20Hz-20kHz Intermodulation distortion Mute according IEC60958 according IEC61937 according IEC61937 amendment 1 1.8 Digital Video Input (IEEE 1394) Implementation according IEEE Std 1394-1995 IEC 61883 - Part 1 IEC 61883 - Part 2 SD-DVCR (02-01-1997) Specification of consumer...
T1
The Digital Board is based on the highly integrated LSI 'Domino' BGA chip (Ball Grid Array), DMN-8602. This IC has an on-chip ATAPI controller and integrates an analog video encorder, and provides build-in support for non-simultaneous progressive and interlaced video output. A 1394 link layer function is also integrated so a simple external physical layer device is required. The DMN-8602 also has a set of integrated USB Physical Layer Interface. The board encodes and multiplexes analogue video...
12011 I13 12013 C13
1206 I7 1207-1 C2 1207-3 G2 1208 A2 4226 F13 4230 I12 5207 E6 5209 E6 7205 H12 F200 A6 F201 C3 F202 C3 F203 C3 F204 C3 F205 E3 F206 E3 F207 G2 F208 G2 F209 G2 F210 H3 F211 H3 F212 C12 F213 C12 F214 D12 F215 D12 F216 E12 F217 E12 F218 E11 F219 F13 F220 F13 F221 H12 F222 H13 F223 I13 F224 I13 F225 H11 F226 I3 F227 I3 F228 I7 F229 I7 F230 I7 F231 I8 F232 I8 F233 I8 F234 I8 F235 I8 F236 I8 F237 I8 F238 I9 F239 I9 F240 I9 F241 H7 F242 H9 F243 H3 F244 H3 F245 I7 F246 I7 F247 I7
3139 785 30981
Safety Information, General Notes & Lead Free Requirements 2. Safety Information, General Notes & Lead Free Requirements Safety regulations require that during a repair Connect the unit to the mains via an isolation transformer. Replace safety components, indicated by the symbol A , only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard. Safety regulations require that after a...
Vgnstby
In Standby mode, STBY control line is low, switching off 3V3SW, 5V, 5N (provision), 5VE, 12V and 12VE supply reducing the power consumption. The Analog board supports 2 possible Tuner Frontend unit namely 1101 - PAL BG,DK and I Broadcast System 1100 - NTSC-M Broadcast System It has a RF IN for antenna connection and RF OUT which provides a RF loop through for connection to the TV. The Frontend 1101 ( Tuner & IF-demodulator ) is controlled by I2C (SCL_5V- and SDA_5V-) lines coming from the...
1101 B10 1111 E10
3169 H13 3171-1 G2 3171-2 G2 3171-3 G2 3178-1 I2 3178-2 I2 3178-3 I2 3178-4 I2 3181-1 G4 3181-2 G4 3181-3 H4 3188-1 I4 3188-2 I4 3188-3 I4 3188-4 I4 4102 B4 5121 F9 5131 G8 5141 G9 5151 H10 5162 H12 5171 I10 5181 I11 6101 C3 7101-1 D5 7101-10 I7 7101-2 A5 7101-3 B12 7101-4 A2 7101-5 F7 7101-6 D2 7101-7 A8 7101-8 F3 7101-9 A12 7105 G12 7111-1 E12 7111-2 F13 F101 B6 F102 B6 F103 B6 T101 B1 T102 B1 T103 B1 T104 B1 T105 B1 T106 B1 T111 E11 T112 E11 T113 E11 T121 A11 T122 B11
O
The sound processing is always done in stereo (that means separate left- and right- channel). The complete selection of audio signal for recording is done by a HEF4052 7301 , which is a dual four-to-one mulitplexer. The input lines for the selector 7301 are coming either from MSP 7500 (AFEL AFER) or cinch rear-in Ext 1 ( AIN1L AIN1R) or cinch rear-in Ext 2 (AIN2L AIN2R) or the cinch front-in (AINFl AINFR). The 7301 controlled via RSA1- and RSA2- signals coming from the MSP 7500 . The MSP acts...
Jcr
Horizontal sync output or digital composite sync output Programmable general-purpose I O Vertical sync output (for modes with dedicated VSYNC) or VBLK output Programmable general-purpose I O Odd even field indicator output. This terminal needs a pulldown resistor. Programmable general-purpose I O Active video indicator output Programmable general-purpose I O IC7501 - Power Distribution Switches
Get Sound
Connect the AUDIO L R (red white) jacks at the back of the DVD recorder to the correspond AUDIO input jacks on a TV, stereo system or receiver. Turn on the connected system and select the appropriate channel. NEED HELP Read the accompanying User Manual or visit our website www.philips.com support 4.1 Dismantling and Assembly of the Set For item numbers please see the exploded view in Chapter 9. 4.1.1 Dismantling of the DVD Loader Tray Cover 1) Inserting a minus screw driver and push the lever...
Cmos
Bus manager contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10-k resistor to a high contender or low not contender . The resistor allows the link-on output to override the input. However, it is recommended that this terminal should be programmed low, and that the contender status be set via the C register bit. If the TSB41AB1 is...
7401
The analogue video input signals CVBS, YC and RGB are routed via the board to connector 1521 and sent to Video Input Processor, TVP5146P 7401 . The digital video input signals from the DV-in on the Front board are routed from connector 1521 via the IEEE 1394 PHY IC 7301 to the Domino chip 7101 . The Video Input Processor encodes the analogue video to digital video stream CCIR656 format . The output stream, named VID_D 9 0 , is then routed to the Domino chip. This IC encodes and decodes the...
