If a worst-case scenario—as shown in Fig. 1.56, which is closer to reality—is assumed, efficiencies are lower. In Fig. 1.56, it is assumed that at turnon, the voltage across the transistor remains at its maximum value (Vdc) until the on-turning current reaches its maximum value of I0. Then voltage starts falling, and to a close approximation, current rise time Tcr will equal voltage fall time. Turnon switching losses will then be

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