Flyback Converters

The flyback converter has long been popular for low-power applications. The major attraction of the flyback topology is its low component count. At higher power levels, the output capacitor ripple current is often too great to deal with using conventional, low-cost capacitors. Dynamic response is also limited in continuous conduction mode, because of a right-half-plane (RHP) zero in the transfer function.

In the flyback topology, energy is stored in a power inductor (which often has multiple windings, as in a transformer) during the on-time of the switch. During the off-time of the switch, the energy is delivered to the load. The flyback topology is often used in both discontinuous and continuous conduction modes and can be successfully controlled using current mode or voltage converters.

A Flyback Subcircuit

A simplified functional schematic diagram of the flyback subcircuit is shown in Fig. 5.1. It is included in the Power IC Model Library for PSpice available from AEi Systems. It is a universal subcircuit that is capable of simulating the flyback regulator in both the continuous and discontinuous modes of operation with either voltage mode or current mode control. The derivation of the model is as follows.

Defined terms

Pin Converter input power VC Offset error amp output

Lm Power transformer NP Power transformer ratio magnetizing

/min Minimum primary Vout Subcircuit output voltage current

Transformer For Igbt

Figure 5.1 Flyback subcircuit schematic that can be used in both voltage and current modes with discontinuous and continuous inductor currents.

/max Peak primary current Fsw Switching frequency n

Efficiency factor Propagation delay MOSFET on-time Converter input voltage

I out Average output current Rb Current transformer burden

NC Current transformer ratio D Converter duty cycle Pout Converter output power

Governing equations

Pout = Pnn

Imax is defined by the control Voltage Vc as

Rb Tm

The MOSFET on-time is calculated as

9 UtLAY

During the MOSFET off-time, the primary current falls as

NP Lm Fsw

Substituting equations,

NP \ Vin (Imax — /min) which can be further simplified as

Vout Np V

Substituting equations,

out 2 VVout Vin Np - Vout and the duty cycle can be calculated as

LmFsw (^max Zmin)

The circuit shown in Fig. 5.2 is a simple representation, using the new subcircuit, of a dual-output flyback converter with a separate transformer winding for voltage regulation. The flyback subcircuit essentially replaces the PWM switch model discussed in Chap. 4.

The results of the gain-phase measurement of the flyback converter are shown in Figs. 5.3 and 5.4 for a 30-mA load and a 1-A load on each output, respectively. The circuit has a bandwidth of 7 kHz with a phase margin of 75° and a 1-A load. At a 30-mA load, the performance is quite different because of the discontinuous operation. The 34 kHz would likely be a problem for most applications. Either the converter would require a preload or the 1-A load bandwidth would have to be reduced. This would sacrifice performance.

Note that L1 and C4 are used to break the loop for the open-loop measurement. Voltage source V4 represents the injection signal. This method allows the DC path to be closed via L1, while the AC information is removed (essentially) by the very low frequency filter created by L1 and C4.

Audio Susceptibility

The same SPICE model can be used to evaluate closed-loop performance parameters, such as audio susceptibility. To use the model for these

X1 FLYBACK

TURNS

100U> R1 450

X1 FLYBACK

TURNS

Self Switching Flyback Converter

C2 450 100U

FLY1: DUAL OUTPUT FLYBACK CONVERTER

.AC DEC 25 100 1MEG

.OPTIONS RELTOL=.01 ITL1=500 ITL2=500 ITL4=500 GMIN=1n

.PROBE

.PRINT AC V(11) VP(11) V(3) VP(3) .PRINT AC V(6)VP(6) .PRINT TRAN V(3) V(18) .PRINT DC V(17)

V1 1 0 28 ; add "AC 1" for Audio Susceptibility Test

X3 2 0 13 4 TURNS Params: NUM=18

X4 9 0 13 4 TURNS Params: NUM=18

X5 0 7 13 4 TURNS Params: NUM=18

X6 3 0 13 4 TURNS Params: NUM=12

D1 9 11 DN5806

D2 18 7 DN5806

C1 11 0 100U

C2 0 18 100U

R1 11 0 15 ; 15 ohms for 1A, 450 for 30ma R2 0 18 15 ; 15 ohms for 1A, 450 for 30ma R3 4 0 1MEG

X7 8 21 0 6 16 14 UC1843AS

VEA 6 60 10m ; Added for convergence at low currents

Figure 5.2 Schematic design and netlist for a dual-output flyback converter.

R4 3 21 8K R5 21 0 2.5K C3 8 12 1N R6 12 21 47K V3 16 0 15

L1 17 60 10 ; 10 for open loop Gain/Phase analysis, 1p for Closed loop

* analysis (Transient or Audio Susceptibility)

C4 15 17 10 ; 10 for open loop Gain/Phase analysis, 1p for Closed loop

* analysis (Transient or Audio Susceptibility) V4 15 0 AC 1

X1 1 0 17 2 5 FLYBACK Params: L=20U NC=100 NP=1 F=250K EFF=1 RB=10

.END

Figure 5.2 (Continued).

evaluations, the inductor, capacitor, and AC voltage source can be left in the circuit. This is accomplished by changing the value of L1 to 1 pH, and C4 to 1 pF. To simulate the audio susceptibility performance, an AC source statement must also be added to the input voltage source, V1.

The results of the audio susceptibility simulation are shown in the graph of Fig. 5.5.

Bode Plot For Mosfet With Gain

1K 10K 100K

Freqency in Hz

Figure 5.3 Gain-phase Bode plot of the dual-output flyback converter with a 1-A load on each output.

1K 10K 100K

Freqency in Hz

Figure 5.3 Gain-phase Bode plot of the dual-output flyback converter with a 1-A load on each output.

360.00 80.000

270.00

40.000

270.00

40.000

90.000

90.000

1K 10K 100K

Freqency in Hz

Figure 5.4 Gain-phase Bode plot of the dual-output flyback converter with a 30-mA load on each output.

Flyback Converter

Freqency in Hz

Figure 5.5 Audio susceptibility simulation results, node 11.

Input Voltage in Volts

Figure 5.6 Graph showing the nonlinear relationship between the input voltage and the control voltage.

Input Voltage in Volts

Figure 5.6 Graph showing the nonlinear relationship between the input voltage and the control voltage.

Feedforward Improvements

The flyback converter has a peak input current that varies with input voltage.

This can be seen by sweeping the input voltage and monitoring the control voltage or the output of the error amplifier (see Fig. 5.6).

Although this curve is not linear, the audio susceptibility of the flyback converter can still benefit from feedforward compensation. This is most easily added via a simple resistor connected from the input voltage to the current sense pin of the PWM IC. We can add a feedforward signal in series with the control pin of the subcircuit to accomplish the same effect.

The schematic showing the incorporation of the feedforward signal is shown in Fig. 5.7.

The improvement in audio susceptibility is graphically shown in Fig. 5.8. Note that the feedforward signal improves the audio susceptibility performance by more than 20 dB. In several applications, I have been able to use this feedforward technique, rather than adding a linear regulator, to obtain the necessary attenuation. There are several benefits. There is no reduction in efficiency performance, as would occur with the addition of a linear regulator. Also, the converter can be made smaller and less expensively without the linear regulator.

Vpl Es2 Power Supply
TURNS

FLY2: FEEDFORWARD SIGNAL .OPTION GMIN=10N .NODESET V(2) = 15.7

.AC DEC 25 100 1MEG

* ALIAS V(5)=D .PRINT AC V(6)VP(6) .PRINT AC V(11) VP(11) V(3) .PRINT TRAN V(3) V(18) V(5) V1 1 0 28 AC 1

X3 2 0 13 4 TURNS Params: NUM=18 X4 9 0 13 4 TURNS Params: NUM=18 X5 0 7 13 4 TURNS Params: NUM=18 X6 3 0 13 4 TURNS Params: NUM=12 D1 9 11 DN5806 D2 18 7 DN5806 C1 11 0 100U C2 0 18 100U

* I1 0 11 pulse 0 0.5 .1u .1u .1u 1m 2m ; use for load step analysis R1 11 0 15

Figure 5.7 Feedforward signal schematic and netlist.

X1 1 0 17 2 5 FLYBACK Params: L=20U NC=100 NP=1 F=250K EFF=1 RB=10

.END

Figure 5.7 (Continued).

Flyback Transient Response

The transient response of the flyback converter is unaffected by the addition of the feedforward signal. The transient response simulation results in Fig. 5.9 show an overlay of a 0.5-A step on the +15-V output with and without the feedforward signal. To calculate the DC output resistance, we use the following equations:

lout 0.833

VD7 V064

Frequency in Hz

Figure 5.8 Graph showing improvement in audio susceptibility.

Frequency in Hz

Figure 5.8 Graph showing improvement in audio susceptibility.

15.082 15.060

15.042 a 15.020

15.002 g 14.980

14.962 14.940

14.922 14.900

2.2000M 2.6000M 3.0000M 3.4000M 3.8000M

Time in Secs

Figure 5.9 Transient response simulation results with the unaffected flyback converter.

= 1 (350 nH) (2.07)2 250kHz + (1.04)2 0.1 + (1.15)2 0.03 2

P 0 188

Reff = -j^ + Rd = —-- + 0.12 = 0.483 + 0.12 = 0.603 n

The resulting 0.6 n is a good approximation of the DC output resistance. Based on our example, the load regulation from 10% to 100% load would be

The actual value that was recorded for the converter was 0.49 V. Obviously, the resistance is nonlinear and dependent upon input voltage, but this is a good estimate.

The calculated output resistance was implemented into this SPICE model in order to get the simulation results of Fig. 5.11.

From the previous simulation, we can obtain the nominal duty cycle of 0.36 with an input voltage of 28 V, or we could calculate it as

The delta inductor current can be calculated on the basis of the output voltage and D':

Ls Fs

The peak secondary current is calculated as

The secondary RMS current can be approximated by

J Tout

The output capacitor RMS ripple current is calculated as

The effects of the diode forward drop can best be approximated by evaluating the difference in forward voltage at two output currents of interest as

The parameters from the power supply design are listed in the following table.

Li

350 ßH

Lout

0.833 A

L s

25 ßH

Fs

250 kHz

ESR

0.03 Œ

DCR

0.1 Œ

D

0.36

D '

0.64

N

1

R eff

0.12 Œ

Simulating Regulation

One of the more difficult simulations to perform is the DC regulation of the flyback converter. The regulation and, more importantly, the cross-regulation of a flyback converter is a function of the parasitic leakage

X1 FLYBACK +15

X1 FLYBACK +15

Schaltplan Bose Model Power Stand

Figure 5.10 Dual-output 15-V power supply schematic.

Figure 5.10 Dual-output 15-V power supply schematic.

inductance of the power transformer, the output rectifier characteristics, and the output capacitor equivalent series resistance (ESR).

In simple terms, these losses can be viewed as linear power losses. Although this is not entirely true, it will generally provide reasonably accurate results. The one characteristic that will not show up is the large voltage at the output under light-load or no-load conditions. This does not generally pose a problem because there is a protection or limiting device (such as a zener diode) present to make this voltage predictable.

The following example is from an actual dual-output 15-V power supply that was designed recently (see Fig. 5.10). Given the following parameters, we will calculate the regulation for incorporation into our SPICE model.

Definitions

L1

Power transformer

/out

Output DC current

secondary leakage

inductance

Ls

Power transformer

Fs

Switching frequency

secondary inductance

ESR

Output capacitor

DCR

Transformer secondary

ESR

resistance

D

Duty cycle

D '

1 Duty cycle

N

power transformer turns ratio

/rms

RMS secondary current

Ipk Peak secondary current

A /1 Secondary inductor current delta Reff Effective average resistance

Rd Effective diode resistance Icap Output capacitor RMS current

The total loss of the secondary can be calculated as floss — 2 T1 If Fs + Ir2ms DCR + Ic2ap ESR

FLY3: FEEDFORWARD SIGNAL

.OPTION RELTOL=.01 ABSTOL=0.1u VNTOL=10u GMIN=10NITL1=500 ITL4=500 .NODESET V(2) = 15.7 .TRAN 10U 4M 2M 1u .PROBE

X3 2 0 13 4 TURNS Params: NUM=18 X4 9 0 13 4 TURNS Params: NUM=18 X5 0 7 13 4 TURNS Params: NUM=18 X6 3 0 13 4 TURNS Params: NUM=12 D1 10 11 DN5806 D2 18 15 DN5806 C1 11 0 100U C2 0 18 100U

I1 0 11 pulse 0 0.5 .1u .1u .1u 1m 2m R1 11 0 15 R2 0 18 15 R3 4 0 1MEG

X7 8 21 0 6 16 14 UC1843AS

R4 3 218K

C3 8 12 1N

R6 12 21 47K

V3 16 0 15

X1 1 0 17 2 5 FLYBACK Params: L=20U NC=100 NP=1 F=250K EFF=1 RB=10

.END

The simulation results are shown in Fig. 5.11 along with the previous transient simulation results in order to see the effect of the output resistance.

2.2000M 2.6000M 3.0000M 3.4000M 3.8000M

Time in Sees

Figure 5.11 Transient analysis that shows the effect of the output resistance.

2.2000M 2.6000M 3.0000M 3.4000M 3.8000M

Time in Sees

Figure 5.11 Transient analysis that shows the effect of the output resistance.

Time Domain Model

The next simulation shows the basic configuration for a transient model of an off-line flyback converter (see Fig. 5.12). The transient model allows us to investigate details within the converter, such as peak switch current, harmonic content, output ripple voltage, and many other phenomena that would not be observable using a state space model.

Although this model is somewhat simplified, it can easily be upgraded even further. Upgrades could include a nonlinear core model for the power transformer, an input EMI filter, multiple outputs, transformer leakage inductance, etc. In most cases, it is recommended that you start with a basic power supply representation such as this and then add the required details. In fact, each piece can be simulated separately before they are all put together. Using this approach you will have more assurance that the final model will converge, and you can make any necessary changes to the subsections by taking advantage of the superior simulation speed. Obviously, as the model complexity increases, the run time will also increase, thus making investigation of the behavior of each subsection more costly.

The simulation results of the transient model are shown in Fig. 5.13.

350V

R14 10K

16.6

r"'

Tran

R13

VOUT6.2

I

50K

DIODE

5.88

Tran

VERR 385M

0

time

R10 3K

LT1243

XFMR

R12 146K

C6 56P

YV(28) VERR

R10 3K

LT1243

4.7NF

C4 1NF

CP VREF FB VCC ISENS OUT RT/CT GND

R9 1K

C4 1NF

4.7NF

XFMR

CP VREF FB VCC ISENS OUT RT/CT GND

R9 1K

DIODE

V(16) VOUT

C2 68UF

R6 45M

LT1243: OFF-LINE FLYBACK CONVERTER *SPICE_NET

.TRAN 0.1US 0.6MS .IMS 10n UIC .PROBE

.OPTIONS RELTOL=.005 ITL4=300

.PRINT TRAN V(9) V(16) V(12) V(17) V(28) V3 2 0 350V R2 16 0 15

R6 3 0 45M

D1 12 16 DIODE OFF

.MODEL DIODE D (TT=1NS CJO=1PF RS=1M) X7 28 21 17 27 0 11 15 25 LT1243 R8 14 0 2.8

R9 17 14 1K

C4 17 0 1NF

R10 27 25 3K

R12 21 28 146K

C6 21 28 56P

Figure 5.12 Schematic for an off-line flyback converter using a PWM IC model capable of showing all key transient effects. The top-level netlist is also shown.

R13 21 16 50K R14 210 10K S9 9 14 11 0 SW

.MODEL SW VSWITCH RON=.1 VON=5 VOFF=3 ROFF=1E6

.END

Figure 5.12 (Continued )

14.5

Figure 5.12 (Continued )

14.5

150U

250U 350U 450U

Time in Secs

550U

150U

250U 350U 450U

Time in Secs

550U

\

\

1 1 1 1

;

tMMM

lAAAAMl

307.69U Time in Secs

Figure 5.13 Transient model results.

Adding Slope Compensation

The schematic in Fig. 5.14 shows the addition of an external ramp to provide slope compensation to the model. The D output of the subcircuit is provided for this purpose. The D output is a voltage equivalent of the duty cycle; so a ramp is defined as K*D, where K is the peak voltage of the ramp at a duty cycle of 1. K can also be described as the slope of the ramp divided by the switching frequency.

Although we do not have access to the internal nodes required to add the ramp, we can rotate it through the comparator and easily add it externally. A nonlinear dependent source is used to provide the multiplication of K and D. The schematic in Fig. 5.15 shows the implementation of the slope compensation ramp that is external to the subcircuit.

Figure 5.15 Schematic of the subcircuit with the addition of an external ramp using a nonlinear dependent source.

Voltage Mode Control

Using a further extension of the circuit shown in Fig. 5.15, voltage mode control (also called duty cycle control) can be implemented. In this case there is no current sensed, so RB would ideally be set to zero. However, RB cannot be set to zero because it would result in a "divide by zero error" within the subcircuit. It can, however, be set to a very low value such as 1 mn or lower, if necessary. Setting K to 1 will result in a duty cycle that is equal to the control voltage, VC. The modulator gain may also be represented in this subcircuit by setting K equal to 1/V-, where Vr is the peak-to-peak voltage of the ramp. Within the subcircuit, VC is bounded between 0 and 1 V. To use this limiting function, it is recommended that you set K to 1 and add the modulator gain externally.

0 0

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