Buffer Amplifier and LowZ Attenuator

The Buffer Amplifier presents a high-impedance, low-capacitance load to the input signal and delivers an accurate replica of that signal to a low-impedance buffer output circuit. The Low-Z output circuit is composed of a 250-i2 voltage-divider network (R139F through R139J) and the Volts/Div Var circuit (R141, C141, and R143). Switch S105B selects the appropriate output from the voltage divider. The Buffer Amplifier contains two paths: a slow path consisting of R116, R117, U120, and R119 in parallel with C119; and a fast path through C121. The signals through both paths are applied to the gate of Q122.

In the slow-path portion, the input signal is divided by ten by the combination of R117 and R116 and is then applied to U120 pin 3. The Buffer Amplifier output signal is also divided by ten by the combination of R139B, R139C, R139D, and R139N. Sufficient dc-gate bias for input FET Q122 is generated by the slow-path circuit to produce a null (zero difference) between pins 2 and 3 of U120. The closed-loop gain of the slow path is matched to the fast-path gain. If the average output voltage from the fast path changes, transconductance amplifier U120 adjusts the dc gate bias on Q122 to keep U120 pin 2 and U120 pin 3 nulled. This action keeps the slow-path and the fast-path gains matched. Resistor R119 isolates the output impedance of U120 from the input of FET Q122. This isolation, in combination with the high input impedance of U120, prevents high-frequency loading of the input signal. Capacitor C119 compensates for the output capacitance of U120.

Step Balance potentiometer R138 (at pin 1 of R139) is adjusted to compensate for input offsets reaching U120 pins 2 and 3 when switching between VOLTS/DIV switch positions.

In the fast path, the input signal is ac-coupled to input FET Q122 through C121. The input FET is arranged in a source-follower configuration used to drive complementary emitter followers Q133 and Q134. The combination of Q125, R126, R131, R132, VR130, and R130 sets a constant current through R125 in the source lead of Q122. The voltage drop across R125 biases Q133 and Q134 for about a 10-mA idle current.

A bootstrap circuit composed of Q139, VR122, and R122 connects the Q122 drain to the Q122 source. This circuit forces the bias voltage across Q122 to remain constant, which in conjunction with the constant bias current supplied by R125, keeps Q122 operating at a constant power level to prevent distortion due to changing signal currents.

Complementary emitter followers Q133 and Q134 supply drive current to the -M, +2.5, and -K> voltage dividers and provide impedance matching between input FET Q122 and the divider network. The bias levels of Q133 and Q134 are stabilized by emitter resistors R139A and R139E respectively. Average voltage changes occurring in the output of Q133 and Q134 are sensed through R139B and R139D which are connected to the point of lowest impedance (the emitters of Q133 and Q134). Resistor R139C provides a path that completes the feedback loop to the slow-path portion of the Buffer Amplifier.

correct deflection factor for the 2m, 5m, and 10m VOLTS/ DIV switch positions. Resistors R146, R147, and R148 act to balance any dc offsets between the X1 and X10 amplifiers. Trace shift occurring when the VOLTS/DIV Variable control is rotated is minimized by resistor R142 which stabilizes the input bias current to U145.

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