Channel Switching Logic Circuit

The Channel Switching Logic circuitry composed of U310A and U317A selects either Channel 1 or Channel 2 and various display modes for crt display via front-panel switches and the X-Y position of the SEC/DIV switch.

When the instrument is not in the X-Y Mode, signal line XY is grounded through contacts on the SEC/DIV switch (Diagram 8). This action establishes LO logic levels on pins C, B, and G of front-panel switch S317 (CH 1-BOTH-CH 2) and on pins C and B of S305 (INT).

Switch S317 selects the vertical channel signal that drives the Delay Line Driver via the Channel Diode Gates. With S317 set to CH 1, a LO is applied to the Set input (pin 4) of U317A. Flip-flop U317A will then be set, and the Q output (pin 5) will be HI. Pin 5 of U317A is the CH 1 Enable signal line, and when it is HI, the Channel 1 vertical signal is gated to the Delay Line Driver. When S317 is set to CH 2, the Reset input of U317A (pin 1) will be held LO through CR705. The CH 2 Enable signal (U317A, pin 5) is then set HI and the Channel 2 vertical signal is gated to the Delay Line Driver.

Setting S317 to the BOTH position removes the LO from both the Set and Reset inputs of U317A. This action allows the channel selected for display to be determined either by the logic level applied to the D input (pin 2) and the clock applied to pin 3 or by the logic level applied to the Set and Reset inputs from the ADD-ALT-CHOP switch.

The ADD-ALT-CHOP switch (S315) is enabled by the LO placed on pins A, C, and F when the CH 1-BOTH-CH 2 switch is set to BOTH. When in ADD, S315 holds both the Set and Reset input of U317A LO through CR706 and CR701 respectively. The Q and Q outputs of U317A will then be HI, and both Channel 1 and Channel 2 vertical signals are gated to the Delay Line Driver. The signal current is summed at the input to the Delay Line Driver, and the resulting oscilloscope Add vertical display is the algebraic sum of the two vertical signals.

The Add Enable circuit, composed of Q316, U197C, and U315A, is activated when both Diode Gates are turned on for an Add vertical display. With the Q and Q outputs of U317A HI, the output of U315A will be LO and transistor Q316 is biased on. The collector of 0316 rises toward +5 V and U197C is biased on. Transistor U197C supplies the additional current required to keep both Diode Gates forward biased and to supply the proper dc level to the Delay Line Driver input. Bypass capacitor C316 prevents switching transients from being introduced into the Delay Line Driver by the Add Enable circuit.

When S315 is set to ALT, a HI is placed on both the Set and Reset Inputs of U317A. Flip-flop U317A will transfer the logic level on the D input (pin 2) to the Q output (pin 5) on each clock-pulse rising edge. Pin 1 of NAND-gate U310A is held HI by the Chop Oscillator output, and pin 2 follows the Alt Sync signal produced by the Holdoff circuitry in the A Sweep Generator (Diagram 5). The output of U310A (pin 3) is therefore an inverted Alt Sync pulse. The signal on the D input of U317A (pin 2) follows the logic level set by the Q output pin. As each clock pulse occurs, the states of the Q and Q outputs reverse (toggle), enabling Channel 1 and Channel 2 Diode Gates alternately with each sweep.

CHOP OSCILLATOR. Setting S315 to CHOP enables the Chop Oscillator and the Chop Blanking circuit. Pins C and D of S315 are connected to place a LO logic level on the Set input (pin 10) of U317B. The Q output of U317B is set HI and the Chop Oscillator is allowed to run. A HI level is present on U310D pin 13 due to C308 being charged to the HI level on U310D pin 11. When pin 12 of U310D also goes HI, the output of U310D goes LO. Capacitor C308 now must discharge to the new dc level. As soon as the charge of C308 reaches the LO threshold level of U310D, the output at pin 11 switches HI again and C308 charges toward the HI logic level (see Figure 3-4).

When the HI switching threshold level is reached, the output of U301D changes state to LO again. This cycle continues at about 500 kHz to produce both the Chop Clock and the Chop Blank signals.

The Chop signal is gated through NAND-gate U310C and applied to U310A pin 1. The Alt Sync pulse on U310A pin 2 is HI (except during holdoff time) so the output of U310A pin 3 is the inverted Chop Oscillator signal on pin 1. This signal is applied to the Clock Input (pin 3) of U317A to drive the Channel Switching circuitry. Since flipflop U317A clocks with rising edges only, the frequency of the chopped channel switching is about 250 kHz.

The signal output from U310C pin 8 is also fed to the Chop Blanking circuit. Capacitor C311 and resistors R310 and R311 form a differentiating circuit that produces positive and negative short-duration pulses when the Chop Oscillator signal changes levels.

The dc level at U310B pins 4 and 5 is set slightly above the HI switching threshold logic by a voltage divider consisting of R310 and R311. Positive pulses from C311 continue to hold U310B above the threshold level, so the output remains LO. Negative pulses from C311 drop below the threshold level of U310B, and the output of U310B switches HI for a duration of about 0.4 (is (see Figure 3-4) to produce the positive Chop Blanking pulse. The Chop Blanking pulse is fed to the Z-Axis Amplifier and is used to prevent display of the transistions when switching between vertical channels.

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