Delay Circuit

The Delay circuit, composed of Q624, Q632, Q644, Q650, Q652, U607D, and associated components, generates the timing and gate signals required to produce the intensified Sweep display and to provide the variable Sweep delay. HORIZONTAL MODE switch S650 controls the display mode (NO DLY, INTENS, or DLY'D), and DELAY TIME switch S660 selects the basic delay time (0.2 ms, 10 jus, or 0.5 ms). The DELAY TIME MULTIPLIER control (R658) increases the possible delay available by up to at least twenty times the basic delay.

NO DLY. With HORIZONTAL MODE switch S650 set to the NO DLY position, the Delay circuit is disabled and the Sweep starts immediately after the Swp Gate signal is produced by U603B at pin 9. Pin D of S650 is open, so pins 4 and 10 of U620 are pulled HI through R608. When the

Swp Gate occurs, pins 1, 2, 5, and 9 of U620 all go HI. The HI on pin 5 is ANDed with the HI on pin 4, and U620 pin 6 goes LO to initiate a Sweep. The output of the Delay circuit is disabled by grounding the base of Q644 through pin A of S650. This action holds the Dly Gate signal at the collector of Q652 at a HI logic level. With the Dly Gate signal HI, a HI is also gated through U620 to pin 8 to bias off CR620. Diode CR622 is then forward biased to enable the Intens Level current from R622 to the Z-Drive line to unblank the crt for the Sweep display.

INTENS. With S650 set to the INTENS position, the Delay circuit is enabled. No delay in the Sweep occurs in this mode, but an intensified zone is displayed. The amount of delay between the start of the Sweep and the start of the intensified zone is determined by the DELAY TIME switch setting and the MULTIPLIER control position.

The intensified zone is generated by gating through U607D to control the Z-Axis gating diodes, CR619 and CR621 (see Figure 3-6). Pin 12 of U607D is pulled HI through R607 as pin H of S650 is open. When the delay time has elapsed, U607D pin 13 is also switched HI (by the Dly Gate signal), and pin 11 goes LO. Diode CR619 becomes reverse biased, and CR621 passes the Intens Level current to the Z-Drive line. The extra current is added to

Figure 3-6. Simplified diagram of the Z-Axis Switching Logic circuit.

the Swp Z-Axis current already present from CR622 to intensify the display. The non-intensified portion of the trace indicates the amount of total delay time.

DLY'D. In this position of HORIZONTAL MODE switch S650, the start of the sweep is delayed by the amount of time established by the Delay circuit. When a trigger signal clocks U603B to produce a HI Swp Gate signal on U603B pin 9, the delay time is started. The HI is applied to the base of Q624 via R613 to bias that transistor off. Transistor Q624 is used as a switch across the delay timing capacitors. When biased on, the transistor keeps the timing capacitors discharged. When the transistor is biased off, the delay timing capacitors are allowed to charge. Both the amount of capacitance and the charging voltage are controlled by DELAY TIME switch S660. The DELAY TIME switch also controls the voltage range applied to MULTIPLIER potentiomter R658.

For the longest delay-time range (0.2 ms), S660 switches C622 in parallel with C624. When switched to the 10-/us delay position, C622 is out of the delay timing circuit. Finally, in the 0.5-/us position, additional charging current is supplied to C664 via R692 to increase the charging rate, and +8.6 V is applied to the MULTIPLIER potentiometer via R600. The increased voltage changes the control range available at the wiper of R658.

At the start of the delay time, U603B pin 8 goes LO. This removes the positive bias from Q632, and the emitter voltage of Q632 becomes near ground potential. As the delay timing capacitor charges, the base of Q632 remains at a constant voltage, therefore the base of Q652 goes negative. When the base of comparator transistor Q652 reaches a more negative level than the base of comparator transistor 0644 (set by the MULTIPLIER control), 0652 starts to switch off and Q644 starts to switch on. The collector voltage drop of 0644 is coupled back to the emitter of Q632 via R641 to complete the switching action. The collector voltage of Q652 rises to a HI logic level which is applied to Sweep Logic Gate U620 on pins 3 and 13. The HI is ANDed with the HI Swp Gate signal already present to produce a LO output at U620 pin 6 and pin 8. The LO at pin 6 initiates a Sweep, and the LO at pin 8 unblanks the crt.

In the DLY'D Mode, pin 12 of U607D is LO, so pin 11 will be HI to bias CR619 on and CR621 off (Figure 3-6). This action prevents intensifying current from reaching the Z-Drive line during the DLY'D Sweep display.

During Sweep retrace time, CR621 is biased off by the HI applied to CR668 from U603B pin 8 to keep the crt blanked off.

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