Internal Trigger Switching Logic

Internal trigger-selection signals to the Trigger Pickoff Amplifier (Diagram 2) are produced in a logic circuit composed of U305B, U305C, U305D, U315B, and U315C. The TRIGGER INT Source switch (S305), in conjunction with CH 1-BOTH-CH 2 switch (S317), determines the internal trigger source selected. When either the CH 1 or CH 2 Internal Trigger signal is selected by S305, the selected channel will be the internal trigger source. When VERT MODE is selected as the internal trigger signal, the position of S317 determines the channel(s) selected as the internal trigger source.

CHANNEL 1 SOURCE. The XY signal line from the A SEC/DIV switch (S630B) applies a LO logic level to INT switch S305 on pins B and C. In the CH 1 position, the LO is coupled from pin C to pin D and applied to U305B pin 4.

The LO is gated through U305B and applied to the CH 1 Trig signal line in a wired-AND connection. The LO from U305B is applied to Q273 in the Channel 2 Internal Trigger Pickoff Amplifier (Diagram 2) to bias it off, thus preventing the Channel 2 signal from being selected. Operation of the Internal Trigger Pickoff Amplifiers is discussed in the "Channel 1 and Channel 2 Preamps" circuit descriptions.

Concurrently, pins 9 and 10 of U305C are pulled HI through R304 and R300 respectively to place a HI at U305C pin 8. The HI from U305C to the wired-AND connection on the CH 2 Trig signal line enables the output of U315B to control the logic level of the CH 2 Trig signal. Control is accomplished by the logic levels on the inputs of U305D, pins 12 and 13.

The LO on U305B pin 4 (placed there by S305) also occurs on U305D pin 13. This ensures a LO at U305D pin 11, which is applied to U315C pin 9 and to U315B pin 5. The logic level applied to U315C pin 9 has no effect on the CH 1 Trig signal because a LO is already present at the wired-AND connection to the signal line. However, the LO applied to U315B pin 5 ensures that the output of U315B is HI. When the CH 2 Trig signal is HI, Q173 in the Channel 1 Internal Trigger Pickoff Amplifier is biased on and the Channel 1 signal is passed to the Internal Trigger Amplifier (Diagram 4).

Figure 3-4. CHOP VERTICAL MODE waveforms.

CHOP OSCILLATOR U310C, PIN 8

*-2/js--

CHOP BLANKING PULSE U310B, PIN 6

THRESHOLD

THRESHOLD

CHOP CLOCK U317A. PIN 3

CH 1 ENABLE U317A. PIN 5

--4/js-»■

CH 2 ENABLE U317A, PIN 6

3826-23

CHANNEL 2 SOURCE. When S305 is set to CH 2, the

LO logic level present on S305 pin B is coupled to pin A and applied to U305D pin 12 and to U305C pin 10. The output of U305C at pin 8 is a LO which is applied to the CH 2 Trig signal line by the wired-AND connection. When the CH 2 Trig signal is LO, the Channel 1 Internal Trigger Pickoff Amplifier is biased off to prevent the Channel 1 signal from reaching the Internal Trigger Amplifier.

The inputs to U305B, pins 4 and 5, are both pulled HI through R305 and R304 respectively, and the HI output from pin 6, applied to the wired-AND connection on the CH 1 Trig signal line, allows U315C to control the CH 1 Trig signal logic level. As described in the preceding "Channel 1 Source" discussion, the logic levels at U305D pins 12

and 13 control the output of U315B. The LO on U305D pin 12 ensures a LO output at pin 11, which is applied to U315C at pin 9. This LO ensures a HI output at U315C pin 8, the CH 1 Trig signal line.

With the CH 1 Trig signal HI, Q273 in the Channel 2 Trigger Pickoff Amplifier is biased on and the Channel 2 signal is passed on to the Internal Trigger Amplifier.

VERT MODE SOURCE. Additional switch settings are involved in determining the internal trigger signal selection when VERT MODE Trigger Source is selected. Both the CH 1-BOTH-CH 2 and the ADD-ALT-CHOP VERTICAL MODE switches establish the vertical signal display and, as such, must also be used to obtain the internal vertical mode trigger signal.

When S305 is set to VERT MODE, the LO logic level on the XY signal line is removed from both U305B pin 4 and from U305D pins 12 and 13, pulling these inputs HI. In either ADD or ALT VERTICAL MODE, U305C pin 9 and U305B pin 5 are also pulled HI whenever a LO is not being applied from S315.

The input conditions just described for U305B, U305D, and U305C allow the logic levels on U315C pin 10 and U315B pin 4 to control the states of the CH 1 Trig and CH 2 Trig trigger-selection signals. Input signals to pins 10 and 4 are obtained from the Channel Enable signals present at pins 5 and 6 of Channel Switch U317A.

When CH 1 Enable is HI (selecting the Channel 1 signal for display), U315C pin 10 is also HI and U315C pin 8 is LO to disable the Channel 2 Trigger Pickoff Amplifier. Concurrently U317A pin 6 applies a LO to U315B pin 4, and the HI output obtained from U315B pin 6 as a result enables the Channel 1 Trigger Pickoff Amplifier.

A CHOP VERTICAL MODE display also uses the sum of the two internal trigger signals, but the switching logic involved is different from the ADD VERTICAL MODE display. With S315 set to CHOP, a LO logic level is applied to U305B pin 5 and to U305C pin 9 from the XY signal line via contacts on S315, S317, and S305. The outputs of both U305C and U305B are LO and are applied to the wired-AND connection on the CH 1 Trig and CH 2 Trig signal lines. These LO signals override the outputs from U315C and U315B to hold the input transistors of both Channel 1 and Channel 2 Trigger Pickoff Amplifiers biased off. Channel 1 and Channel 2 Trigger signals are summed as described previously for the ADD VERTICAL MODE display.

X-Y MODE. When the SEC/DIV switch is set to X-Y, the Channel 2 signal is selected as the input to the Vertical Output Amplifier to provide the X-Axis deflection. The Channel 1 Trigger signal provides the X-Axis signal to the XY Amplifier (Diagram 7) via the Internal Trigger Amplifier. Therefore, the Trigger Switching Logic circuit must have inputs that enable the Channel 1 Trigger Pickoff Amplifier.

For ALT VERTICAL MODE displays, the output states of Channel Switch S317A are switched alternately, at the end of each sweep, in synchronization with the Alt Sync signal. Therefore, on alternate sweeps, the logic levels on U315C pin 10 and on U315B pin 4 also change states.

When the Channel 1 signal is being displayed, the Channel 1 Trigger signal is selected as the internal source. For Channel 2 signal displays, the Channel 2 Trigger signal is selected.

An ADD VERTICAL MODE display causes both pin 5 and pin 6 of U317A to be HI (see "Channel Switching Logic" discussion for a description of the circuit operation). The sum of the two channel vertical signals is displayed, and the sum of the two channel trigger signals is used as the internal trigger signal.

The LO logic level signal supplied by the XY signal line to S305 and S317 is removed by switching contacts on the SEC/DIV switch. Concurrently, a LO logic level is placed on the XY signal line by contacts on the SEC/DIV switch. The LO on the XY line is applied to the Reset input of U317A to select the Channel 2 signal for display. This LO is also applied to U305B pin 4 and to U305D pin 13 via U305A to set up the Trigger Switching Logic that enables the Channel 1 Trigger Pickoff Amplifier.

A LO on U305B pin 4 ensures that the output of U305B pin 6 is a LO, which is applied to the CH 1 Trig signal line to disable the Channel 2 Trigger Pickoff Amplifier. The LO on U305D pin 13 is gated to U315B pin 5. With U315B pin 5 LO, the output of U315B will be a HI that, when ANDed with the HI present from U305C pin 8, enables the Channel 1 Trigger Pickoff Amplifier.

Summation is accomplished by the HI logic levels from U317A pins 5 and 6 causing both the CH 1 Trig and CH 2 Trig signals to go LO. With the input transistors to both Trigger Pickoff Amplifiers biased off, additional circuitry within the Trigger Pickoff amplifiers biases on the pickoff transistors for both Channel 1 and Channel 2 (see the Channel 1 and Channel 2 Preamplifier circuit descriptions.

0 0

Post a comment