Sweep Logic

Following the sweep completion, a finite time is required to discharge the timing capacitor. The Sweep Logic circuit is prevented from responding to a trigger signal during this time by the Holdoff circuit. The end of sweep (and start of the holdoff period) is determined by the End-of-Sweep Comparator (Q640).

The Sweep ramp waveform is applied to the base of Q640 through both a voltage divider and a biasing network composed of R637, R638, and C637. When the ramp amplitude reaches the threshold level of Q640, the collector of Q640 goes LO, and a LO is placed on both U640B pin 11 and U607C pin 10. The output of U607C goes HI, and the positive feedback supplied to the base of Q640 through R639 speeds up the change of state of Q640. By reinforcing the switching action of Q640 in this manner, noise occurring at the threshold level of Q640 is overridden.

The sweep holdoff period commences when the LO from Q640 is applied to pin 11 of monostable multivibrator U640B. The Q output on pin 9 goes LO and remains LO for a length of time determined by the RC timing components connected between pins 14 and 15 of U640B.

Holdoff time can be varied from the normal period by using VAR HOLDOFF control R557. Potentiometer R557

A TRIGGER

TRIGGER_ .

TRIGGER_ .

A TRIGGER

SWP GATE -I

U620,

PIN 6 u

SWEEP Q631, COLLECTOR

END OF SWEEP Q640 COLLECTOR

START OF HOLDOFF

U640B PIN 9

END OF HOLDOFF

HOLDOFF U603 PINS 1 & 13

SWP GATE U603 PIN 9

U620,

PIN 8

ALT SYNC CR644, ANODE

DLY END U620 PINS 3 & 13

LO FOR DELAY TIME

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