1 Configuration

DC system,250W, short arc length 3mm. To use light effectively in the tilt projection system, the light axis is arranged to face upward. Elliptical reflector converges light emitted from the metal halide-lamp, thereby creating light beams parallel with light axis and illuminating the beams to the liquid crystal panel. Converges the parallel light beams from the reflector in direction of focal point and effectively transmits the beams through 1.3 inch liquid...

1 Digital Circuit Operation

In the digital circuit, the following operations are carried out video signal double speed conversion enlargement process (NTSC signal), sync generation Various kinds of timing signal generation necessary for liquid crystal panel driving and on-screen signal generation. Fig. 6-1 shows the digital circuit block diagram. This unit uses a liquid crystal panel with 832 x 624 pixels. Basically, the effective pixel number (scanning line number) in the vertical direction is specified as the display...

1 Lamp High Voltage Power Supply

The lamp high voltage power supply receives a DC220 to 390V (primary side) from the system power supply and provides a DC voltage (50 to 70Vdc at ever turning on the lamp) to turn on the lamp. Fig. 2-1 shows the block diagram. The DC voltage is supplied to CN701 from the main power supply unit through an interlock switch (S023). This voltage becomes AC input x 202 ( 340V for AC120V input) when the lamp is off. CN703 is a connector for the lamp on control signal input and lamp off control signal...

1 Operating Description

The base current at start-up passes through QM02, RM04 - RM06 and then flows into the base of QM03. QM02 works as the ON OFF switch for start-up operation and turns ON when the base voltage develops L. When the base voltage develops H (12V), QM02 turns off and QM03 oscillation stops. A current flows into QM01 and RM03 only when the start-up operation is carried out, thus improves the start-up characteristics by increasing the base current of QM03. Especially, this circuit takes effective under...

1 Outline

This circuit is described using G process as an example and composed of level shifter, gamma (g), black limiter, inverted signal amplifier, sample & hold circuit and liquid crystal panel. This circuit is described using G process as an example and composed of level shifter, gamma (g), black limiter, inverted signal amplifier, sample & hold circuit and liquid crystal panel.

1 System Outline

The system microcomputer has features as shown below. In considering easy maintenance for specification modification, etc. an external program ROM is employed. The program is also developed in considering use of structured notation, parts modularity, and multi filling system. Major functions of the system microcomputer are as follows. (1) System control Power reset process Nonvolatile memory control process Remote control reception process RS-232C transmission and reception process Status...

10 Video Mode Fetch Process

In the video mode fetch process, a status fetch IC Q543 (CXA1315M) fetches the status in the read mode of I2C bus (Custom 45). Fig. 5-9 shows the I2C bus read timing diagram. Table 5-4 shows the contents of the video mode signals and the logic. Contents of the video mode signals and the logic Contents of the video mode signals and the logic

11 Video System Control Process

In the video system control process, control signals are supplied to various video system process ICs through P501. Fig. 5-10 shows the I2C bus timing diagram and table 5-5 shows the contents of process in each kind of IC. Table 5-5 Contents of process in each kind of IC Table 5-5 Contents of process in each kind of IC Brightness, contrast, RGB gain, Video RGB input switching Input signal (Video Audio), Video S terminal input Color signal process (3D Y C separation) Sync detection process...

12 Panel System Control Process

The panel system control process supplies various control signals to the panel system control ICs through P901. Table 5-6 shows the contents of process in each kind of IC. Fig. 5-11 shows the M62358FP control bus timing diagram, Fig. 5-12 does the CXD2442Q control bus timing diagram, Fig. 5-13 does the SYG read mode bus timing diagram and Fig. 5-14 does the SYG write mode bus timing diagram. Table 5-6 Contents of process in each kind of IC Table 5-6 Contents of process in each kind of IC Screen...

13 Various Display Modes

In this system, various LED display patterns are provided in relation to the display modes shown in Table 5-7. Operations from AC on to power on and power off will be given below. Data of the non-volatile memory are checked at the AC on, and all the LED are turned on in red in the initial use. In second or later use, all the LEDs are turned on in green and the unit enters the standby status. In the standby status, only the STANDBY ON LED is turned on in orange, and the main power is off and the...

14 Applicable Signal

Quite a signals are used as the applicable signals in the preset mode (standard value) as shown in table 5-10. For the signals not fit to the preset modes, a user mode is provided. In the preset modes, the applicable signals are based on the VESA standard, so the sample frequency (CLOCK adjustment in the panel menu) is not used, but the adjustment is allowed only in the user mode. In the user mode, the signal line number is detected to allow the separate adjustment in the VGA system (basically...

15 Rs232c Control Method

Table 5-9 RS-232C connection signals Signals are connected to the RS-232C connector in a straight format as shown in Table 5-9 RS-232C connection signals. This is because a crossing connection is provided inside the unit. Communication conditions are set to meet the conditions given in Table 5-10. Table 5-9 RS-232C connection signals Table 5-10 RS-232C communication conditions Table 5-10 RS-232C communication conditions Transmission speed 9600 baud, No parity, data length 8 bit, Stop bit 1 bit...

16 Rs232c Command List

Table 5-11 shows the RS-232C command list. As a return value for a specified command received, an acknowledgment signal (ACK 06h) is output when the command is correctly received within the operating conditions, or a non-acknowledgment signal (NAK 16h) is output without the operating condition. Nothing is output if reception terminates abnormally. When sending a command, leave the interval for at least 100 ms. Moreover, a longer process time is necessary at the power on or off, and input...

2 Circuit Description

The following description will be given assuming that Vbe of transistor is 0.7V. This circuit is composed of the emitter follower Q945, full feedback unit gain amplifier Q946 - Q950, and the current source circuit of sub bright for Q951 - Q953. The circuit operates to vary only the DC level of the input signal and develops the signal with only the DC level shifted from the input signal at Q949. The shift level is determined by the current flowing into R976. When a triangular waveform of 2.3V -...

2 Circuit Description 21 Clamp Circuit

A D converter converts the video signal demodulated to RGB signals in the digital signals to perform digital-process. The video signal is clamped to fit the reference level of the A D converter. The clamp is of a pedestal clamp type and uses the reference level voltage of A D converter. The actual clamp voltage potential is approx. 1.2 V. Fig. 6-4 shows the clamp circuit for G signal section. Either CXD1175AM manufactured by SONY or TLC5510INS manufactured by TI is used for A D converter (QX16,...

2 Description About Circuit Operation

The surge absorber circuit consists of protection element (varistor) and spark gap on the pattern surface on the PC board, making it possible to protect the power from being destroyed by lighting stroke and impulse invaded from external or from malfunction. Secondary rectification smoothing circuit Secondary rectification smoothing circuit The noise filter circuit only protects the noise generated by the power source from leaking out to AC line and from entering of the external noise inside the...

4 Nonvolatile Memory Process

In the non-volatile memory process, data reading and writing for various adjustments are carried out on the non-volatile memory (QL03 CAT24C16) as shown in Fig. 5-1. When the power (AC) is on, all the adjustment data are read out by the system microcomputer (QL01) at the timing shown in the read out timing diagram of Fig. 5-3 (A), thereby realizing the previous status. When saving the data, all the adjustment data are written by the system microcomputer (QL01) at the timing shown in the timing...

5 Remote Control Reception Process

In the remote control reception process, a remote control unit (CT-9888) connected to the remote control terminal emits a remote control signal and a remote control signal receive section (ZL002) on the front panel or a remote control signal receive section (ZL003) on the rear panel decodes the signal. Each remote control signal decoded is mixed through the connectors of PL010 or PL011 and fed to the system microcomputer (QL01) through a buffer QL07 (MC74 HC14AF). Fig. 5-4 shows the remote...

6 Rs232c Transmitreceive Process

In the RS-232C transmit receive process, an RS-232C signal entered through the RS-232C connector (D-SUB 9P) on the rear panel is decoded in the RS-232C interface (QL05 MAX232CPE), and fed to the system microcomputer (QL01) through PL005. Fig. 5-5 shows the RS-232C signal timing diagram. Tw 1 9600 104.17 s Communication conditions 9600 pds, non-polarity, 8bits length, 1 stop Fig. 5-5 RS-232C signal timing diagram

7 Status Read Process

In the status read process, two data fetch ICs, QL11, QL12 (MC74HC165AF) as shown in Fig. 5-1, read the status. Fig. 5-6 Data fetch timing diagram Table 5-2 Contents of the status read signals and the logic Fig. 5-6 shows a data fetch timing diagram. QL11 reads panel key status and QL12 does various status. Table 5-2 shows the contents of the status read signals and the logic.

8 Status Display Process

In the status display process, a status display IC QL10 -1 . i i i i i i i i . . . . . i- (MC74HC595AF) shown in Fig. 5-1 displays the status. SWC UUUUUUUU Fig. 5-7 shows the data display timing diagram. Table 5-3 shows the contents of the status display signals and the logic. Fig. 5-7 Data display timing diagram Table 5-3 Contents of the status display signals and the logic

9 Onscreen Display Process

In the on-screen display process, control signals are supplied to the OSD display IC QX43 (mPD6453) through P901, and the OSD display IC generates character display signals at the timing determined by VD, HD and clock supplied to the IC separately. Fig. 5-8 shows the timing diagram for the on-screen control signals. (A) 1 byte command OSL _First byte_Second byte_ SD D7MD5XD4XD3XD2XD1XDQ D7XD6XD5XD4XD3XD2XD1XDQ OSL _First byte_Second byte_Second byte_ OSD p7)(d6)(d5)(d4)(d3)(d2)(d1 XD07 Fig. 5-8...

Section Vi

RGB Signal 1-3. NTSC Signal 1-4. PAL SECAM Signal Input 6-4 2. CIRCUIT DESCRIPTION 6-5 2-1. Clamp 2-2. A D 2-3. 2-4. PLD 2-5. D A Sync Process IC 6-13 2-7. PLL Circuit 2-8. PLL Circuit Generation Circuit 6-17 Generation Circuit 6-23 1. Generation Circuit (SG) 8-2 1-2. Pre-amp Circuit (PRO, ENC, 1-4. Power Supply SECTION IX FLUORESCENT LAMP INVERTER CIRCUIT 9-1 1. OPERATING DESCRIPTION 9-2 2-1. Fluorescent does not turn on 9-3 3. CIRCUIT DIAGRAM 9-4

Video Signal Process

Video Signal Demodulation Block 7-2 1-4. Audio Signal Amplification Block 7-2 2. INPUT OUTPUT SIGNAL SWITCH CIRCUIT 7-3 2-1. Audio Video Signal Switch Circuit 7-3 3. VIDEO DEMODULATION 3-1. YC Separation 3-2. Video Color Circuit 7-6 3-3. Luminance (Y) Signal Process Circuit 7-7 3-4. Color Signal Process Circuit 7-8 3-5. Picture Sharpness Correction Circuit 7-8 3-6. RGB 3-7. Audio 4. RGB SIGNAL PROCESS 4-1. RGB Signal SW 4-2. Video RGB Signal SW Section 7-12 4-3. RGB...

3 Video Demodulation Block

This circuit separates Y and C signals from a composite video signal. Fig. 7-4 shows the pin configuration of TC9090AN and Fig. 7-5 shows the block diagram. The composite video signal enters pin 3. A fsc (3.58 4.43MHz) output from the video color IC enters pin 19 and is converted into a 4fsc of the drive clock frequency inside the IC. The composite video signal entered is processed at a rate of the clock frequency of the IC and output as Y and C signal. Vrefh (1) VSS1 (T) ADIN (T) VDD1 4 Vrefl...

4 Rgb Signal Process Circuit 41 RGB Signal SW Section

The RGB signals are entered from a high density D-SUB 15 pin. The signals are divided into two systems through buffers, the one is input to RGB video SW section and the other is output from RGB output terminal after the signal is amplified by 6 dB (75W drive) for RGB outputs. The RGB output signals are always developed as long as signals are being supplied to the RGB input terminal. The sync signal is corresponding to HD, VD, CS (composite sync) and SYNC ON G. The HD, VD, CS are connected to...

[j

Fig. 6-12 Memory control signal timing diagram MB40958PF is a 8-bit 3ch bi-polar D A converter which works at a conversion rate of 60 M sample s. The pin configuration of the IC is shown in Fig. 6-13, the pin functions are in table 6-6 and its internal block diagram is in Fig. 614. The peripheral circuit of the D A converter is shown in Fig. 6-15. The reference voltage output terminal is connected to the reference voltage input terminal (pin 37) and supplied with 3V. Accordingly, the output...

2 Inputoutput Signal Switch Circuit

The I O signal switch circuit selects signals (video and audio ) entered and feeds them to later stages and each output terminal. Fig. 7-2 shows the switching section of the audio video signal switch circuit. 2-1. Audio Video Signal Switch Circuit The signal switching for the audio video signal entered is carried out by Q200 SW IC (TA1218N). Each I O signal is connected to Q200 as shown in Fig. 7-2. Each I O control is entirely carried out through I2C bus. The composite video signal is input to...

U U U U U U It

Fig. 6-10 Write control signal timing diagram EPM7032LC44-10 is used for PLD (QX41). This PLD is based on CMOS EE-PROM and a device which can be written and erased electrically. The block diagram of the circuit written in the IC is shown in Fig. 6-11 and its pin configuration is shown in table 6-5. The IC is composed of the divider circuit, which operates PLL circuit (2), and memory control circuit. In the divider circuit, the clock signal divided in four is output in the standard mode...

3 Power Supply Reset Process

In the power supply reset process, a watch dog timer MM1096BS is used as a power supply reset IC QL04 as shown in Fig. 5-1. The reset IC QL04 accepts a clock pulse signal for the watch dog timer which is sent from WDT terminal of the microcomputer, determines the microcomputer is in an abnormal status due to some reason if the clock signal does not exist for about 1s , and sends a reset signal to the RESET terminal of the system microcomputer QL01 . Fig. 5-2 shows the MN1096BS reset timing...

Section I

DESCRIPTION ABOUT CIRCUIT OPERATION 1-2 2-1. Surge Absorber 2-2. Noise Filter 2-3. Rush Current Protection Circuit 1-3 2-4. Smoothing Rectifying Circuit 1-3 2-5. Inverter Circuit 2-6. Primary Control Smoothing Circuit 1-5 2-8. 6V Detection Protection Circuit 1-5 Protection 2-11. Output ON OFF Circuit 1-6 2-12. ON OFF Control Circuit 1-6 1. LAMP HIGH VOLTAGE POWER 1. 2. CIRCUIT DESCRIPTION 4-2 2-1. Level Shifter Q945 - Q953 4-2 2-2. Gamma c Q965 - Q968, R1044 4-4...